Task s in testbench

N

nezhate

Guest
Hi all !
I'm wrting a testbench that uses a task for reading data from file.
when I wrote this task I used a parameter. Is it possible to change
the value of this parameter when calling this task in the testbench?
Thanks
 
On 12 Mar 2007 00:26:41 -0700, "nezhate"
<mazouz.nezhate@gmail.com> wrote:

Hi all !
I'm wrting a testbench that uses a task for reading data from file.
when I wrote this task I used a parameter. Is it possible to change
the value of this parameter when calling this task in the testbench?
Thanks
Click to expand...
No, not if it's really a *parameter*. Parameters in Verilog are
constants at run-time.

If the task has *arguments*, then of course you can change those
call by call.

However, it's fairly easy to change a parameter for each new run
of your simulation. Most simulators have a command-line option
to override generics (VHDL) or parameters (Verilog) when you
load the simulation. Alternatively, you can use the macro
mechanism, something like this:

`define DATAFILE "stuff/datafile.txt"

module testbench;
...
parameter datafile_name = `DATAFILE;
...
task read_data;
integer f_id;
f_id = $fopen(datafile_name, "r");
....

Now, when you compile this simulation, you can redefine the
macro on the compilation command line: the option is
usually +define+param=new_value or something similar.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Mar 12, 2:08 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
On 12 Mar 2007 00:26:41 -0700, "nezhate"

mazouz.nezh...@gmail.com> wrote:
Hi all !
I'm wrting a testbench that uses a task for reading data from file.
when I wrote this task I used a parameter. Is it possible to change
the value of this parameter when calling this task in the testbench?
Thanks

No, not if it's really a *parameter*. Parameters in Verilog are
constants at run-time.

If the task has *arguments*, then of course you can change those
call by call.

However, it's fairly easy to change a parameter for each new run
of your simulation. Most simulators have a command-line option
to override generics (VHDL) or parameters (Verilog) when you
load the simulation. Alternatively, you can use the macro
mechanism, something like this:

`define DATAFILE "stuff/datafile.txt"

module testbench;
...
parameter datafile_name = `DATAFILE;
...
task read_data;
integer f_id;
f_id = $fopen(datafile_name, "r");
...

Now, when you compile this simulation, you can redefine the
macro on the compilation command line: the option is
usually +define+param=new_value or something similar.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...


There are two ways to override parameters but both are compile time
options and not runtime to save elaboration problems

One is
vcs -parameters <filename >

where ther file will have
assign param_name value


or

vcs -pvalues+<param_na>=<value>


Hope that helps
-Parag
 
On Mar 12, 3:26 am, "nezhate" <mazouz.nezh...@gmail.com> wrote:
Hi all !
I'm wrting a testbench that uses a task for reading data from file.
when I wrote this task I used a parameter. Is it possible to change
the value of this parameter when calling this task in the testbench?
Thanks
Click to expand...
There may be different options depepending on how "stable" is the data
currently represented in your task with parameter.

1. If data can change frequently, set it from the task inputs.
2. If data is more stable, but can be changed in the same test case,
use external-to-task configuration register, updated using another
configuration task, for example:

//-----------------------------
reg mode = 0;

task config_mode;
input my_mode;
mode = my_mode;
end

task my_task;
....
if (mode) [do_something]
else [do_something_else]
....
//-----------------------------

With configuration registers, there is an option to change
configuration during the test case run. Also, it is easy to implement
configuration modes looping&randomization as well as to collect
configuration modes functional coverage metrics.

Regards,
-Alex
 
On Mar 13, 4:41 pm, "Alex" <agnu...@gmail.com> wrote:
On Mar 12, 3:26 am, "nezhate" <mazouz.nezh...@gmail.com> wrote:

Hi all !
I'm wrting a testbench that uses a task for reading data from file.
when I wrote this task I used a parameter. Is it possible to change
the value of this parameter when calling this task in the testbench?
Thanks

There may be different options depepending on how "stable" is the data
currently represented in your task with parameter.

1. If data can change frequently, set it from the task inputs.
2. If data is more stable, but can be changed in the same test case,
use external-to-task configuration register, updated using another
configuration task, for example:

//-----------------------------
reg mode = 0;

task config_mode;
input my_mode;
mode = my_mode;
end

task my_task;
...
if (mode) [do_something]
else [do_something_else]
...
//-----------------------------

With configuration registers, there is an option to change
configuration during the test case run. Also, it is easy to implement
configuration modes looping&randomization as well as to collect
configuration modes functional coverage metrics.

Regards,
-Alex
Click to expand...
thanks for all for answering me.
another question:
what can I do in the case when one or multiple input ports of task has
a variable number of bits?
exemple:
task read;
input [length_x-1:0] port_a; //length_x,length_y,length_z:values
that
//must be passed to task from the
outside
input [length_y-1:0] port_b;
output [length_z-1:0] port_c;
......
......
end
endtask

thanks.
 
On Mar 14, 2:11 am, "nezhate" <mazouz.nezh...@gmail.com> wrote:
On Mar 13, 4:41 pm, "Alex" <agnu...@gmail.com> wrote:



On Mar 12, 3:26 am, "nezhate" <mazouz.nezh...@gmail.com> wrote:

Hi all !
I'm wrting a testbench that uses a task for reading data from file.
when I wrote this task I used a parameter. Is it possible to change
the value of this parameter when calling this task in the testbench?
Thanks

There may be different options depepending on how "stable" is the data
currently represented in your task with parameter.

1. If data can change frequently, set it from the task inputs.
2. If data is more stable, but can be changed in the same test case,
use external-to-task configuration register, updated using another
configuration task, for example:

//-----------------------------
reg mode = 0;

task config_mode;
input my_mode;
mode = my_mode;
end

task my_task;
...
if (mode) [do_something]
else [do_something_else]
...
//-----------------------------

With configuration registers, there is an option to change
configuration during the test case run. Also, it is easy to implement
configuration modes looping&randomization as well as to collect
configuration modes functional coverage metrics.

Regards,
-Alex

thanks for all for answering me.
another question:
what can I do in the case when one or multiple input ports of task has
a variable number of bits?
exemple:
task read;
input [length_x-1:0] port_a; //length_x,length_y,length_z:values
that
//must be passed to task from the
outside
input [length_y-1:0] port_b;
output [length_z-1:0] port_c;
......
......
end
endtask

thanks.
Click to expand...

Then you use parameters LENGTH_X, LENGTH_Y, LENGTH_Z in the module
where your tasks reside. If you are planning to change these values
during test case run, define task inputs and outputs with the maximum
possible bit width.

-Alex
 
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