N
Nicolas Moreau
Guest
Hey everyone, I'm kinda a newbie in VHDL programming. And I don't know
what this error means in my case, here is what I have :
type tab_aud_samp is array (NATURAL range <> of std_logic_vector(31
downto 0);
function clear_table(h : tab_aud_samp) return std_logic_vector is
variable aux : std_logic_vector (31 downto 0);
begin
aux := X"00000000";
for i in 0 to h'length-1 loop
h(i) <= aux;
end loop;
return aux;
end clear_table;
I didn't know how to clear this table in only one clock some other
way. And it tells me that when I do
h(i) <= aux;
"Target of signal assignment is not a signal"
Do you know what it means ? What I should do ?
Thanks a lot.
Nicolas
what this error means in my case, here is what I have :
type tab_aud_samp is array (NATURAL range <> of std_logic_vector(31
downto 0);
function clear_table(h : tab_aud_samp) return std_logic_vector is
variable aux : std_logic_vector (31 downto 0);
begin
aux := X"00000000";
for i in 0 to h'length-1 loop
h(i) <= aux;
end loop;
return aux;
end clear_table;
I didn't know how to clear this table in only one clock some other
way. And it tells me that when I do
h(i) <= aux;
"Target of signal assignment is not a signal"
Do you know what it means ? What I should do ?
Thanks a lot.
Nicolas