t flip flops

[danaitsa_thebest@hotmail.]

hi to everyone...well I feel that I don't know much about
flip-flops...I've got to do a vhdl programme that will describe the
behavior of a t flip-flop...but I don't know how to link the q(t+1)
input with the q(t) output...and that because it is in force the
following:

T(input) Clock Q(t+1)-->output
0 1 Q(t)
1 1 not Q(t)

how can I do that programme?

 

[KJ]

Homework is hell sometimes.

Perhaps pick up a book on VHDL and take a look at what VHDL calls a
'process'....no more hints now

 

[danaitsa_thebest@hotmail.]

Well what I have done so far is the following:
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY Dflipflop IS
PORT (Clock,Resetn,T:IN STD_LOGIC;
Q:BUFFER STD_LOGIC);
END Dflipflop;

ARCHITECTURE Behavior OF Dflipflop IS
BEGIN
PROCESS
BEGIN(Clock,Resetn)
IF Resetn='0' THEN
Q<='0';
ELSIF T='1' AND (Clock'EVENT AND Clock='1') THEN
Q<=NOT Q;
ELSE
Q<=Q;
END IF;
END PROCESS;
END Behavior;
However I feel that is not correct as doesn't link the Q(t+1) value
with Q(t) one.(t=time)
So how can I create in VHDL Q(t+1) instance?
I searched a lot but I did not find anything.

 

[danaitsa_thebest@hotmail.]

Well what I have done so far is the following:
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY Dflipflop IS
PORT (Clock,Resetn,T:IN STD_LOGIC;
Q:BUFFER STD_LOGIC);
END Dflipflop;

ARCHITECTURE Behavior OF Dflipflop IS
BEGIN
PROCESS
BEGIN(Clock,Resetn)
IF Resetn='0' THEN
Q<='0';
ELSIF T='1' AND (Clock'EVENT AND Clock='1') THEN
Q<=NOT Q;
ELSE
Q<=Q;
END IF;
END PROCESS;
END Behavior;
However I feel that is not correct as doesn't link the Q(t+1) value
with Q(t) one.(t=time)
So how can I create in VHDL Q(t+1) instance?
I searched a lot but I did not find anything.

 

[danaitsa_thebest@hotmail.]

Because of a mistake notice that entity is not Dflipflop but Tflipflop.

 

[Peter]

ENTITY Dflipflop IS
PORT (Clock,Resetn,T:IN STD_LOGIC;
Q:BUFFER STD_LOGIC);
END Dflipflop;

Shall be Tflipflop, as already said.

ELSIF T='1' AND (Clock'EVENT AND Clock='1') THEN

This statement creates a gated clock (or more likely an error message).
Modify it to:

elsif rising_edge(clk) then
if T='1' then
.....

to keep the design synchronous.

/Peter

 

[Thomas Stanka]

Hi,

danaitsa_thebest@hotmail.com schrieb:
[..]

ELSIF T='1' AND (Clock'EVENT AND Clock='1') THEN
Q<=NOT Q;
ELSE
Q<=Q;
END IF;
END PROCESS;
END Behavior;
However I feel that is not correct as doesn't link the Q(t+1) value
with Q(t) one.(t=time)
So how can I create in VHDL Q(t+1) instance?
I searched a lot but I did not find anything.

Why do you think, Q(t+1) is not linked with Q(t)? Just accept that t
increase by one with each rising edge of Clk.

Someone called Thebest should know that vhdl didn't require Q<=Q inside
a clocked process and a sequential process should always be:

IF Resetcondition THEN -- e.g. reset='0'
....
ELSIF rising_edge(Clk) THEN -- clk'event and clk='1' is ok, but old
style
....
END IF;

 

[kunal]

do this way, i think its better for u
library ieee;
use ieee.std_logic_1164.all;
entity tff is
port(t,clock, reset : in std_logic;
q : inout std_logic);
end entity tff;
architecture behavioral of tff is
begin
tflip : process(clock,reset) is
begin
if (reset = '1') then
q <= '0';
elsif (clock'event and clock = '1' ) then
q <= t xor q;
end process tflip;
end architecture behavioral;

it will work properly. when u design ff then try with charactristic
equation like jk ff or t ff as above.
the above code is in vhdl-93 syntax.

 

[danaitsa_thebest@hotmail.]

Iam afraid that although the T flip-flop's net works fine with the use
of an xor synthesis,something like the following is not correct:

begin
if (reset = '0') then
q <= '0';
elsif rising_edge(Clk) then
q <= t xor q;

 

[radarman]

I believe Kunal's code is correct - run it through a simulator.

When t is low, q will get simply get the old value on the next clock
edge. When t is high, q will get the inverse of its old value on the
next clock edge. As long as t is high, q will toggle on every clock.
Thus, t effectively becomes the clock enable.

This is another way of looking at the problem that is logically
equivalent. (and in fact closer to what the synthesis tools will reduce
it to)

tflip: process( reset, clock)
begin
if (reset = '1') then
q <= '0';
elsif (clock'event and clock = '1' ) then
if( t = '1')then -- T is now used as a classic clock enable in
this example
q <= not q;
end if;
end if;
end process tflip;

 

[danaitsa_thebest@hotmail.]

My Tflipflop's net looks like this:
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY Tflipflop IS
PORT (Resetn,Clock,T:IN STD_LOGIC;
Q:BUFFER STD_LOGIC);
END Tflipflop;

ARCHITECTURE Behavior OF Tflipflop IS
BEGIN
PROCESS(Clock,Resetn)
BEGIN
IF (Resetn='0') THEN
Q<='0';
ELSIF rising_edge(Clock) THEN
IF T='1' THEN
Q<=NOT Q;
END IF;
END IF;
END PROCESS;
END Behavior;
However the simulation result is not correct.Should I give a value at
reset during the simulation prrocess or not?

 

[radarman]

Use an intermediate signal, instead of directly using the output. It is
illegal to drive signals or variables in an architecture with an entity
output.

In your case, define a signal q_out, replace all the Q's in your
architecture, and add a line somewhere outside of the process for Q <=
q_out. That should clear up your simulation problem.

 

[Peter]

If you dont give it a reset you will get X forever...
(The inverse of X is also X....)

/Peter

 

[KJ]

It is illegal to drive signals or variables in an architecture with an > entity output.

But 'q' is defined in the entity as 'buffer' not 'out so what is there
is valid. Since he doesn't say what is 'not correct' about the
simulation it is impossible to say much further.

KJ

 

[danaitsa_thebest@hotmail.]

Goodmorning,
Iam so sorry for not mentioning the problem in simulation process.Well
q should normally change condition from 0 to 1 (and the opposite) when
t=1 and at the same time clock=1(asynchronous design).But something
like that does not happen in my simulation process.(q changes condition
wherever it likes.)
Danai

 

[Peter]

Your last proposal is NOT asynchronous.

I suppose you have used BUFFER for Q because you must be able to read Q
inside the process.
As discussed many times in this group, BUFFER shall be avoided.

BUFFER can be avoided if you change the output signal to OUT and gives
it another name e.g. Q1.
Outside the process you just assign Q1 <= Q.

/Peter

 

[danaitsa_thebest@hotmail.]

Thank you Peter for your advice I haven't forgot it...!In order to make
my design asychronous should I do something like the following:
ARCHITECTURE Behavior OF Tflipflop IS
SIGNAL Q_OUT:STD_LOGIC;
BEGIN
PROCESS(Clock,Reset)
BEGIN
IF (Reset='0')
Q_OUT<='0';
ELSIF T='1' THEN
IF rising_edge(Clock) THEN
Q_OUT<= NOT Q_OUT;
ENF IF;
END IF;
END PROCESS;
Q<=Q_OUT;
END Behavior;

 

[Peter]

Hi,

Dont make it asynchronous! Keep it synchronous to avoid all kind of
problems.
What I meant was:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY Tflipflop IS
PORT (Resetn,Clock,T:IN STD_LOGIC;
Q1:OUT STD_LOGIC); -- Not BUFFER!
END Tflipflop;


ARCHITECTURE Behavior OF Tflipflop IS

Signal Q : std_logic; -- Internal dummy signal

BEGIN
PROCESS(Clock,Resetn)
BEGIN
IF (Resetn='0') THEN
Q<='0'; -- Asynchronous reset
ELSIF rising_edge(Clock) THEN -- Synchronous part below..
IF T='1' THEN
Q<=NOT Q;
END IF;
END IF;
END PROCESS;

Q1 <= Q;

END Behavior;

/Peter

 

[danaitsa_thebest@hotmail.]

Thanks all of you,I managed to complete the task at last...Thank you!!!!