Sythesis vs. Simulation

[Mike]

Hi

I have some piece of code that should only be used for simulation & not
for sythesis. Is there any way to tell Xilinx XST that it should ignore
some lines of code for mapping the description onto the slices?

THanks
Mike

 

[Mike Treseler]

Mike wrote:

I have some piece of code that should only be used for simulation & not
for sythesis. Is there any way to tell Xilinx XST that it should ignore
some lines of code for mapping the description onto the slices?

http://groups.google.com/groups/search?q=vhdl+%22synthesis+translate%22

 

[Tricky]

On 7 Jul, 21:32, Mike <mike...@yahoo.com> wrote:

Hi

I have some piece of code that should only be used for simulation & not
for sythesis. Is there any way to tell Xilinx XST that it should ignore
some lines of code for mapping the description onto the slices?

THanks
Mike

The synthesis or synopsis directives, that are pretty much industry
standard, thus:

--synthesis translate_off
.....
the code you want the synthesiser to ignore goes here
.....
--synthesis translate_on

(Feel free to replace sythesis with synopsis)