sythesis question

[Jason Zheng]

Is this synthesizable?

wire empty;
reg [1:0] ptr;
reg [3:0] isEmpty;

assign empty = isEmpty[ptr];

....

always (posedge clk)
if (rst) begin
ptr <= 0;
isEmpty <= 0;
end
else begin
ptr <= ...
isEmpty <= ...
end


thanks,

 

[Kelvin]

Try this segment:

//--------------------------
reg empty;

always @ (ptr or isEmpty)
begin
case(ptr)
2'b00: empty <= isEmpty[0];
...
endcase
end
//-------------------------

Kelvin




"Jason Zheng" <jzheng@jpl.nasa.gov> wrote in message
news:ce476j$8e6$1@nntp1.jpl.nasa.gov...

Is this synthesizable?

wire empty;
reg [1:0] ptr;
reg [3:0] isEmpty;

assign empty = isEmpty[ptr];

...

always (posedge clk)
if (rst) begin
ptr <= 0;
isEmpty <= 0;
end
else begin
ptr <= ...
isEmpty <= ...
end


thanks,

 

[John_H]

If you're wondering if you get an asynchronous reset in a clocked register,
you might be slightly off. The code you have is synthesizable (if you
include the @ that you probably forgot to copy) but your resets will be
synchronous. If that's what you want, great.

always @(posedge clk) // clocked register, synchronous reset
always @(posedge clk or posedge rst) // async reset
if( rst ) ...


always
"Jason Zheng" <jzheng@jpl.nasa.gov> wrote in message
news:ce476j$8e6$1@nntp1.jpl.nasa.gov...

Is this synthesizable?

wire empty;
reg [1:0] ptr;
reg [3:0] isEmpty;

assign empty = isEmpty[ptr];

...

always (posedge clk)
if (rst) begin
ptr <= 0;
isEmpty <= 0;
end
else begin
ptr <= ...
isEmpty <= ...
end


thanks,

 

[Jonathan Bromley]

On Mon, 26 Jul 2004 17:21:39 -0700, Jason Zheng <jzheng@jpl.nasa.gov>
wrote:

Is this synthesizable?

wire empty;
reg [1:0] ptr;
reg [3:0] isEmpty;

assign empty = isEmpty[ptr];

[...]

Yes. It represents a 4-input multiplexer, with
"ptr" feeding the 2-bit binary-coded selector input.
As far as I know, every synthesis tool accepts this.

Is there anything that leads you to suspect the contrary?
--
Jonathan Bromley, Consultant

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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jason Zheng]

Jonathan Bromley wrote:

On Mon, 26 Jul 2004 17:21:39 -0700, Jason Zheng <jzheng@jpl.nasa.gov
wrote:


Is this synthesizable?

wire empty;
reg [1:0] ptr;
reg [3:0] isEmpty;

assign empty = isEmpty[ptr];


[...]

Yes. It represents a 4-input multiplexer, with
"ptr" feeding the 2-bit binary-coded selector input.
As far as I know, every synthesis tool accepts this.

Is there anything that leads you to suspect the contrary?
Great, I've always had doubts about it since I've never had a systematic

training in verilog. Sometimes I get confused about what might cause
problems and what won't.