Sytem Verilog, strings, force question

[David Rogoff]

Here's a weird one. I'm working on converting some old test code that
used the typical 'reg [n*8:1] pretend_im_a_string' to actual System
Verilog string variables. Mostly it's working, but I have a case in
which there's a string down inside a module and the testbench was
forcing it.

The old code was something like this:
force tb.mod0.string_reg = 40'h48454c4c4f";
which I changed to
force tb.mod0.really_a_string = "HELLO";

However, vcs really doesn't like this:

Error-[DTIDCIL] Dynamic type in declarative context

file.v, 917

"force tb.mod0.really_a_string = "HELLO";"

Argument: tb.mod0.really_a_string

String may not be used in declarative context.

Any ideas on this? S.V. issue? VCS issue?

Thanks,

David

 

[Amal]

On Apr 26, 9:52 pm, David Rogoff <da...@therogoffs.com> wrote:

Here's a weird one.  I'm working on converting some old test code that
used the typical 'reg [n*8:1] pretend_im_a_string' to actual System
Verilog string variables. Mostly it's working, but I have a case in
which there's a string down inside a module and the testbench was
forcing it.

The old code was something like this:
force tb.mod0.string_reg = 40'h48454c4c4f";
which I changed to
force tb.mod0.really_a_string = "HELLO";

However, vcs really doesn't like this:

Error-[DTIDCIL] Dynamic type in declarative context

file.v, 917

"force tb.mod0.really_a_string = "HELLO";"

  Argument: tb.mod0.really_a_string

  String may not be used in declarative context.

Any ideas on this?  S.V. issue?  VCS issue?

Thanks,

 David

Try the hierarchical assignment without the force. Maybe that works?

-- Amal

 

[www.testbench.in]

On Apr 27, 8:25 am, Amal <akhailt...@gmail.com> wrote:

On Apr 26, 9:52 pm, David Rogoff <da...@therogoffs.com> wrote:





Here's a weird one.  I'm working on converting some old test code that
used the typical 'reg [n*8:1] pretend_im_a_string' to actual System
Verilog string variables. Mostly it's working, but I have a case in
which there's a string down inside a module and the testbench was
forcing it.

The old code was something like this:
force tb.mod0.string_reg = 40'h48454c4c4f";
which I changed to
force tb.mod0.really_a_string = "HELLO";

However, vcs really doesn't like this:

Error-[DTIDCIL] Dynamic type in declarative context

file.v, 917

"force tb.mod0.really_a_string = "HELLO";"

  Argument: tb.mod0.really_a_string

  String may not be used in declarative context.

Any ideas on this?  S.V. issue?  VCS issue?

Thanks,

 David

Try the hierarchical assignment without the force.  Maybe that works?

-- Amal

If really_a_string has automatic life, then procedural continuous
assignments are not allowed to use on it as per LRM.


- Gopi Krishna
- For SV/VMM/OVM tutorial --> www.testbench.in

 

[David Rogoff]

On 2010-04-26 22:59:08 -0700, www.testbench.in said:

On Apr 27, 8:25 am, Amal <akhailt...@gmail.com> wrote:
On Apr 26, 9:52 pm, David Rogoff <da...@therogoffs.com> wrote:
Here's a weird one.  I'm working on converting some old test code that
used the typical 'reg [n*8:1] pretend_im_a_string' to actual System
Verilog string variables. Mostly it's working, but I have a case in
which there's a string down inside a module and the testbench was
forcing it.

The old code was something like this:
force tb.mod0.string_reg = 40'h48454c4c4f";
which I changed to
force tb.mod0.really_a_string = "HELLO";

However, vcs really doesn't like this:

Error-[DTIDCIL] Dynamic type in declarative context
file.v, 917
"force tb.mod0.really_a_string = "HELLO";"
  Argument: tb.mod0.really_a_string
  String may not be used in declarative context.

Any ideas on this?  S.V. issue?  VCS issue?

If really_a_string has automatic life, then procedural continuous
assignments are not allowed to use on it as per LRM.

I couldn’t get it to work and modified the code to use a parameter so I
could so a defparam instead of the force to override the value for one
instantiation.