Sytem date

[Monika Talwar]

Hi all,
Is there any way to extract system date during run time from VHDL simulation?
I am using Modelsim. I dont want to use PLI or any

Thanks in advance
With warm regards
Mona

 

[Tim Hubberstey]

Monika Talwar wrote:

Hi all,
Is there any way to extract system date during run time from VHDL simulation?
I am using Modelsim. I dont want to use PLI or any

I'm not sure exactly what you want here but I'll take a stab at it
anyway.

ModelSim's command language is Tcl and is a powerful language in its own
right. You can print the date to the transcript file using:

clock format [clock seconds]

You can also have it accessible to your testbench and/or embed it in the
..wlf file by defining a 112-bit signal in your VHDL testbench, lets call
it date_time, and executing the following from the Tcl prompt (main
window) before you start your simulation:

force date_time 16#[clock format [clock seconds] -format
"%Y%m%d%H%M%S"]

This will assign the hex value of the date/time, in yyyymmddHHMMSS
format, to the date_time vector. You can then add this vector to your
wave window or use it inside your testbench. If you want to update this
vector as simulation progresses, you need to check out the "when"
command.

Note that this method is NOT portable to other simulators.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[Srinivasan Venkataramanan]

Hi,
Check out HDL FAQ section of noveldv.com (rather a small one as of now) at
http://www.noveldv.com/verif/hdl_faq/index.html

HTH,
Srinivasan

--
Srinivasan Venkataramanan
Senior Verification Engineer, Intel Bangalore, India
Co-Author of: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
Edition,
2004 isbn 0-9705394-6-0, Ben Cohen, Srinivasan & Ajeetha

http://www.noveldv.com
I don't speak for Intel

"Monika Talwar" <monikatalwar@hotmail.com> wrote in message
news:e71b773.0402110127.265c4231@posting.google.com...

Hi all,
Is there any way to extract system date during run time from VHDL
simulation?
I am using Modelsim. I dont want to use PLI or any

Thanks in advance
With warm regards
Mona