Guest
hi i am new to SystemVerilog. any one gv me the example of using class
in SystemVerilog code..
in SystemVerilog code..
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S
Swapnajit Mittra
Guest
Look at:
http://www.project-veripage.com
There are tutorials on class type variables and on
many other SystemVerilog syntaxes.
http://www.project-veripage.com
There are tutorials on class type variables and on
many other SystemVerilog syntaxes.
Guest
hi,
thanx for ur valuable reply. currently i am using cadence IUS 5.5,
this version doesn't support features like class,struct,union etc..
actually i have to generate the packet using Systemverilog.can u
help me out ??
thanx for ur valuable reply. currently i am using cadence IUS 5.5,
this version doesn't support features like class,struct,union etc..
actually i have to generate the packet using Systemverilog.can u
help me out ??
S
Swapnajit Mittra
Guest
Can you clarify what you mean by you will 'have to generate the packet
using Systemverilog'? When your simulator does not support it, it is a
bit hard to use a data structure.
- Swapnajit.
--
SystemVerilog, DPI, Verilog PLI and all other good stuffs.
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using Systemverilog'? When your simulator does not support it, it is a
bit hard to use a data structure.
- Swapnajit.
--
SystemVerilog, DPI, Verilog PLI and all other good stuffs.
Project VeriPage: http://www.project-veripage.com
For subscribing to the mailing list:
<URL: http://www.project-veripage.com/list/?p=subscribe&id=1>