SystemVerilog: type conversion overloading similar to C++?

A

Amal

Guest
I did a quick search and browsed through the SystemVerilog LRM, but I
could not find anything about this.

How does one create a type conversion (type of overloading) for a
class? Something like this is C++:

class String
{
public:
String( char* cp ); // Constructor
operator const char*() const; // Conversion operator to
const char*
};

operator const char*() const converts objects of type String to char *

Is there an equivalent in SystemVerilog? Can someone show me a small
example please?

-- Amal
 
On Jan 19, 4:39 am, Amal <akhailt...@gmail.com> wrote:
I did a quick search and browsed through the SystemVerilog LRM, but I
could not find anything about this.

How does one create a type conversion (type of overloading) for a
class? Something like this is C++:

class String
{
public:
String( char* cp ); // Constructor
operator const char*() const; // Conversion operator to
const char*
};

operator const char*() const converts objects of type String to char *

Is there an equivalent in SystemVerilog? Can someone show me a small
example please?

-- Amal
Click to expand...
Do you mean cast?
 
On Jan 20, 9:38 am, Enchanter <ensoul.magaz...@gmail.com> wrote:
On Jan 19, 4:39 am, Amal <akhailt...@gmail.com> wrote:



I did a quick search and browsed through the SystemVerilog LRM, but I
could not find anything about this.

How does one create a type conversion (type of overloading) for a
class? Something like this is C++:

class String
{
public:
String( char* cp ); // Constructor
operator const char*() const; // Conversion operator to
const char*
};

operator const char*() const converts objects of type String to char *

Is there an equivalent in SystemVerilog? Can someone show me a small
example please?

-- Amal

Do you mean cast?
Click to expand...
It is like a cast, but it's basically type conversion defined in the
class for objects of that type to another type. Say, you can use
these objects in expressions, if you define type conversion to
standard types.

-- Amal
 
On Jan 18, 3:39 pm, Amal <akhailt...@gmail.com> wrote:
I did a quick search and browsed through the SystemVerilog LRM, but I
could not find anything about this.

How does one create a type conversion (type of overloading) for a
class?

Is there an equivalent in SystemVerilog?  Can someone show me a small
example please?
Click to expand...

I believe you can use the bind statement to overload the assignment
operator between two types. The bound function would then be used as
a conversion for either an explicit cast or implicit conversion due to
assignment. This can only be done if there is not already a built-in
rule for conversion between the two types.

You should be able to find an example under overloading, which is 8.16
in the 2005 LRM.
 
On Jan 21, 2:18 pm, sh...@cadence.com wrote:
On Jan 18, 3:39 pm, Amal <akhailt...@gmail.com> wrote:

I did a quick search and browsed through the SystemVerilog LRM, but I
could not find anything about this.

How does one create a type conversion (type of overloading) for a
class?

Is there an equivalent in SystemVerilog? Can someone show me a small
example please?

I believe you can use the bind statement to overload the assignment
operator between two types. The bound function would then be used as
a conversion for either an explicit cast or implicit conversion due to
assignment. This can only be done if there is not already a built-in
rule for conversion between the two types.

You should be able to find an example under overloading, which is 8.16
in the 2005 LRM.
Click to expand...
How does one overload a type conversion. That basically my question
on the syntax. Can you show me an example?

The LRM describes this as:

overload_declaration ::=
bind overload_operator function data_type function_identifier
( overload_proto_formals ) ;
overload_operator ::= + | ++ | - | - - | * | ** | / | % | == | != |
< | <= | > | >= | =
overload_proto_formals ::= data_type {, data_type}

I am not overloading an operator. I need a type conversion.

I thought of something like:

bind <What_Do_I_Bind_It_To> function <Type_To_Convert_To>
convertToNewType();
return <this.value cast to new type>;
endfunction

I don't quite get the syntax right or it is another construct I need
to use. Not sure if this is possible.
-- Amal
 
On Jan 21, 10:06 pm, Amal <akhailt...@gmail.com> wrote:
On Jan 21, 2:18 pm, sh...@cadence.com wrote:



On Jan 18, 3:39 pm, Amal <akhailt...@gmail.com> wrote:

I did a quick search and browsed through the SystemVerilog LRM, but I
could not find anything about this.

How does one create a type conversion (type of overloading) for a
class?

Is there an equivalent in SystemVerilog? Can someone show me a small
example please?

I believe you can use the bind statement to overload the assignment
operator between two types. The bound function would then be used as
a conversion for either an explicit cast or implicit conversion due to
assignment. This can only be done if there is not already a built-in
rule for conversion between the two types.

You should be able to find an example under overloading, which is 8.16
in the 2005 LRM.

How does one overload a type conversion. That basically my question
on the syntax. Can you show me an example?

The LRM describes this as:

overload_declaration ::=
bind overload_operator function data_type function_identifier
( overload_proto_formals ) ;
overload_operator ::= + | ++ | - | - - | * | ** | / | % | == | != |
| <= | > | >= | =
overload_proto_formals ::= data_type {, data_type}

I am not overloading an operator. I need a type conversion.

I thought of something like:

bind <What_Do_I_Bind_It_To> function <Type_To_Convert_To
convertToNewType();
return <this.value cast to new type>;
endfunction

I don't quite get the syntax right or it is another construct I need
to use. Not sure if this is possible.
-- Amal
Click to expand...
Is this possible? I would appreciate any feedback.

-- Amal
 
On Thu, 24 Jan 2008 15:24:34 -0800 (PST),
Amal <akhailtash@gmail.com> wrote:

Is this possible? I would appreciate any feedback.
Click to expand...
According to the LRM, yes, exactly as Steven Sharp indicated.

Something like this...

// Two different struct types, NOT assignment compatible
typedef struct { .... } S1;
typedef struct { .... } S2;

// Conversion function between them
function S2 conv_S1_to_S2(S1 s);
S2 result;
... // whatever code you need here
... // to convert 's' to 'result'
return result;
endfunction

// Overload the assignment operator
bind = function S2 conv_S1_to_S2(S1 s);

The tool I've just tried this on doesn't support it;
maybe I can try some other tools tomorrow.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Fri, 25 Jan 2008 14:02:56 -0800 (PST),
Amal <akhailtash@gmail.com> wrote:

I think I got the syntax correct now., but does anyone know if
Modelsim supports operator overloading yet? vlog chokes on bind
keyword!
Click to expand...
vlog -sv does *not* choke on "bind", but rather on "bind =".
Binding of instances *is* supported in all the major simulators
now, but binding (overloading) of operators apparently is not -
I tried it today in recent versions of three major tools, and
NONE of them supports it.

I have never heard anyone mention the operator overloading
feature of SV in papers, promotional material or anything
else. Strange; it is an interesting and powerful feature,
and could help to bring Verilog towards the level of power
and flexibility of VHDL for synthesisable designs.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Jan 24, 6:45 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
On Thu, 24 Jan 2008 15:24:34 -0800 (PST),

Amal <akhailt...@gmail.com> wrote:
Is this possible? I would appreciate any feedback.

According to the LRM, yes, exactly as Steven Sharp indicated.

Something like this...

// Two different struct types, NOT assignment compatible
typedef struct { .... } S1;
typedef struct { .... } S2;

// Conversion function between them
function S2 conv_S1_to_S2(S1 s);
S2 result;
... // whatever code you need here
... // to convert 's' to 'result'
return result;
endfunction

// Overload the assignment operator
bind = function S2 conv_S1_to_S2(S1 s);

The tool I've just tried this on doesn't support it;
maybe I can try some other tools tomorrow.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
I think I got the syntax correct now., but does anyone know if
Modelsim supports operator overloading yet? vlog chokes on bind
keyword!

-- Amal
 
On Jan 25, 5:25 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
On Fri, 25 Jan 2008 14:02:56 -0800 (PST),

Amal <akhailt...@gmail.com> wrote:
I think I got the syntax correct now., but does anyone know if
Modelsim supports operator overloading yet? vlog chokes on bind
keyword!

vlog -sv does *not* choke on "bind", but rather on "bind =".
Binding of instances *is* supported in all the major simulators
now, but binding (overloading) of operators apparently is not -
I tried it today in recent versions of three major tools, and
NONE of them supports it.

I have never heard anyone mention the operator overloading
feature of SV in papers, promotional material or anything
else. Strange; it is an interesting and powerful feature,
and could help to bring Verilog towards the level of power
and flexibility of VHDL for synthesisable designs.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
I was very surprised as well. Especially, once I saw the new OVM.
They have classes for comparing DUT outputs against a reference
model. They created two different classes for the comparison. One
for comparing built-in data types (ovm_in_order_built_in_comparator)
and one for comparing classes (ovm_in_order_class_comparator).

Then I wondered why not use operator overloading and write wrapper
classes for basic data types (something similar to build-in int and
class Int in C#) that can be used where primitive data types are going
to be treated as classes. Actually I wrote these primitive data-type
wrappers, so that I can use just the class comparator for everything.
And that is why this question came up.

I do not know how could Verilog/SystemVerilog people go without
operator overloading. I hope vendors implement it soon.

-- Amal
 
On Fri, 25 Jan 2008 18:44:54 -0800 (PST),
Amal <akhailtash@gmail.com> wrote:

[using OVM]
Then I wondered why not use operator overloading and write wrapper
classes for basic data types (something similar to build-in int and
class Int in C#) that can be used where primitive data types are going
to be treated as classes. Actually I wrote these primitive data-type
wrappers, so that I can use just the class comparator for everything.
Click to expand...
OVM already has ovm_built_in_* (* = clone, comp, converter, pair)
wrapper classes for exactly this purpose. They take a built-in
type as a parameter.

I do not know how could Verilog/SystemVerilog people go without
operator overloading. I hope vendors implement it soon.
Click to expand...
I agree it would be nice; but it's only syntactic sugar. You
can easily use functions instead, of course.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
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