Systemverilog Truss/Teal usage in industry?

H

Helpme

Guest
How many people use Truss/Teal versus Synopsys's VMM and Mentor/Cadence's
OVM?
I got the impresssion Synopsys VCS simulator is the 'gold standard' as far
as Systemverilog goes,
but the other vendors have (finally) caught up to the point where verif
engineers can get real
work done in Systemverilog.
 
On Dec 5, 8:11 am, "Helpme" <hel...@nowhere.net> wrote:
How many people use Truss/Teal versus Synopsys's VMM and Mentor/Cadence's
OVM?
I got the impresssion Synopsys VCS simulator is the 'gold standard' as far
as Systemverilog goes,
but the other vendors have (finally) caught up to the point where verif
engineers can get real
work done in Systemverilog.
Click to expand...

I would think that Mentor would have an issue with your VCS being
SystemVerilog Gold standard. They have the most extensive language
support, but that is their fight.

Judging from the traffic I would have to say that VMM has a stronger
following then AVM/OVM which has a stronger following the Teal/Truss.
Now I have looked at all three. I am considering Teal/Truss for my
next project. Why -- because I have done the VMM thing and it is OK
but I want to see what others have to offer. My next project will be
done using Modelsim (maybe Questa depending upon the necessity for
SVTB). Teal/Truss is free and looks to offer a lot of what I get from
SVTB without SV (or with it if I want). I have talked to the Teal/
Truss developers a couple of times and they are very supportive of
folks using it and expanding it's behavior. All good things.

I real insteresting thing is running Teal/Truss without a simulator.
That is build an executable model of your verification platform before
you have RTL. This is interest me greatly as often the RTL is late
and it seems the Verification cannot be easily proven without the
RTL. So many things to consider.

So Gold Standard is hard to place right now. VMM has great support
from Synopsys to those that have VCS license. AVM/OVM are supported
by Cadence and Mentor if you have NCSIM or Questa license. Teal/Truss
are open source and don't require a simulator right off the bat to
investigate it and hooks to all those simulators; i.e. simulator
independent. It is well supported by the developers.

Check out www.verificationguild.com for more information about
Hardware based Verificaton, it is where the verification folks meet
and has a lot of traffic about the topic you just raised!

TomT...
 
I am not against Teal/Truss and all of these VLs but I'm wondering why
don't you folks just use SystemC which is open-source and a stand-
alone simulator with a better quality and maintenance, clear standard
and strong EDA vendor support when comsimulation with HDL?
Just curious.

Regards,
Chris
 
Hi Chris,

Teal/Truss and VMM are not Verification Languages but verification
frameworks (classes and conventions) built within a language. SystemC
in turn is a library but not a verification framework and out-of-the-
box doesn't solve many verification problems.

The reason Robert and I wrote Teal/Truss through PLI/VPI is that we
consider SystemC to be clunky for verification. But that said, we are
working on a SystemC version of Teal. I have done it before (for a
private contract) and then truss sits on top, unmodified.

SystemC provides a great interconnect to Verilog and VHDL HDLs. The
Teal/SystemC version will use that and then get rid of the silly IN/
OUT concept of ports. Heck if we as verification engineers cannot get
wire directions correct, we have big problems! SystemC's heritage was
to be a hardware language, but this is a step backwards for
verification.

Teal will remove the SystemC wire splitting issues and present a vreg
that provides subscripting to get a subrange of bits as a vreg. Teal's
vreg is a multibit thing sort of like sc_logic, except not templated.
It's funny, one of our early versions of vreg was templated exactly
like sc_logic, but we quickly realized that was a mistake.

Teal/SystemC will use SystemC's dynamic threads, so SC_THREAD/
SC_METHOD and subclassing from a SC_MODULE are not needed. You can
start threads whenever you want!

We try not to be negative, but we believe that the "hardwarednes"
together with clumsy port binding and extreme templating of SystemC
has done more to harm C++ adoption than help.

There are other features, like Teal's logger, memory management, and
parameters that SystemC does not have and are needed for verification.

Robert and I are happy to answer and questions about teal/truss. There
are hundreds of pages of documentation as well as a forum on
trusster.com .

Take Care,
Mike
mike <> trusster <> com



On Dec 10, 1:06 am, krzysztof.kono...@gmail.com wrote:
I am not against Teal/Truss and all of these VLs but I'm wondering why
don't you folks just use SystemC which is open-source and a stand-
alone simulator with a better quality and maintenance, clear standard
and strong EDA vendor support when comsimulation with HDL?
Just curious.

Regards,
Chris
Click to expand...
 
I'm not sure of the general adoption level of Teal/Truss, but at my
Silicon Valley startup we are using the SystemVerilog version in
multiple testbenches. I selected it primarily because we have a multi-
simulator environment, and it has worked fairly seamlessly between
simulators. Truss/Teal is more lightweight than VMM and AVM/OVM, and
it allows more flexibility on how to construct a testbench. I would
say the companion book is needed to understand it completely, just as
with VMM/AVM/OVM.

Disadvantages? Well the C++ heritage of Teal/Truss is apparent, and
it avoids relying on the SystemVerilog constraint solver. I have
constructed our testbenches slightly differently than they recommend
to utilize it more, even though the authors have their (philosophical)
reasons for avoiding it.

I wouldn't say that Teal/Truss is always a better choice than VMM/AVM/
OVM, but I trust it more than a framework from a simulator vendor. If
we had 100% VMM code and Synopsys raised the simulator price when we
renewed, we'd be stuck. AVM/OVM may be more portable (I haven't used
it), but I believe Teal/Truss' flexibility allows you to construct a
better testbench with less overhead.
 
Hi,


I investigated teal/truss, found teal package is most useful,
like parameter,memory, it give me some inspire. we can use parameter
class to implement RAL like machanism to test/monitor registe,not
sure.

when investigate vmm, vmm is well organized.
the most suprising me is its vmm_log class, so complex,:), is it
useful??

I investigate its "callback", I was very eagerly to know it before.I
think i got its idea, it also gave me some inspire.
its code like :
if (callback_enable)
execution call back

callback_enable is set/clear using registe_callback/
unregister_callback,

hehe, simple coding,complex concept.


I think vmm is more suitable for unit test,
doest fit big design, for it can not avoid compile time when
trunaround testcase. teal have parameter maybe can avoid trunaroud
time.

also I would like see vmm to opensource like teal/avm.

actually I always prefer c++ and systemC, for c++ have so many
opensource package, if everyone know c++ well, I dont see any market
to systemverilog. when talk with others, nobody support my idea, :-(,I
am sure this is also cadence's advance verification methodology idea.
so,systemC ,ius support better than vcs, ius support mix verilog/
systemC in any hierarchy to support it "advance verification
methodology", but this is lacked in vcs.




teal/truss have the same user interface between c++/systemC/
systemverilog, right? if yes this is a big outcoming.now vmm only in
systemVerilog.
I will use teal/vmm in my next verification task.

vcs is not "golden standard", I always call it a xxx for its obviously
bugs.

here I have a question, how do see class property in waveform?
I always display it. EDA vendor is so silent for this requirement in
their document.

sorry for any words that are not accurate.

Best Regards,
maxwell
 
On Dec 5, 11:11 pm, "Helpme" <hel...@nowhere.net> wrote:
How many people use Truss/Teal versus Synopsys's VMM and Mentor/Cadence's
OVM?
I got the impresssion Synopsys VCS simulator is the 'gold standard' as far
as Systemverilog goes,
but the other vendors have (finally) caught up to the point where verif
engineers can get real
work done in Systemverilog.
Click to expand...


Hi,


I investigated teal/truss, found teal package is most useful,
like parameter,memory, it give me some inspire. we can use parameter
class to implement RAL like machanism to test/monitor registe,not
sure.

when investigate vmm, vmm is well organized.
the most suprising me is its vmm_log class, so complex,:), is it
useful??

I investigate its "callback", I was very eagerly to know it before.I
think i got its idea, it also gave me some inspire.
its code like :
if (callback_enable)
execution call back

callback_enable is set/clear using registe_callback/
unregister_callback,

hehe, simple coding,complex concept.


I think vmm is more suitable for unit test,
doest fit big design, for it can not avoid compile time when
trunaround testcase. teal have parameter maybe can avoid trunaroud
time.

also I would like see vmm to opensource like teal/avm.

actually I always prefer c++ and systemC, for c++ have so many
opensource package, if everyone know c++ well, I dont see any market
to systemverilog. when talk with others, nobody support my idea, :-(,I
am sure this is also cadence's advance verification methodology idea.
so,systemC ,ius support better than vcs, ius support mix verilog/
systemC in any hierarchy to support it "advance verification
methodology", but this is lacked in vcs.




teal/truss have the same user interface between c++/systemC/
systemverilog, right? if yes this is a big outcoming.now vmm only in
systemVerilog.
I will use teal/vmm in my next verification task.

vcs is not "golden standard", I always call it a xxx for its obviously
bugs.

here I have a question, how do see class property in waveform?
I always display it. EDA vendor is so silent for this requirement in
their document.

sorry for any words that are not accurate.

Best Regards,
maxwell
 
Hi Maxwell,

teal/truss have the same user interface between c++/systemC/
systemverilog, right?
Click to expand...

Yes, will allowances for the differences between the two languages.

Robert and I are here to help you in any way we can.

Take Care,
Mike <> trusster <> com


On Dec 18, 9:45 pm, maxwell...@gmail.com wrote:
On Dec 5, 11:11 pm, "Helpme" <hel...@nowhere.net> wrote:

How many people use Truss/Teal versus Synopsys's VMM and Mentor/Cadence's
OVM?
I got the impresssion Synopsys VCS simulator is the 'gold standard' as far
as Systemverilog goes,
but the other vendors have (finally) caught up to the point where verif
engineers can get real
work done in Systemverilog.

Hi,

I investigated teal/truss, found teal package is most useful,
like parameter,memory, it give me some inspire. we can use parameter
class to implement RAL like machanism to test/monitor registe,not
sure.

when investigate vmm, vmm is well organized.
the most suprising me is its vmm_log class, so complex,:), is it
useful??

I investigate its "callback", I was very eagerly to know it before.I
think i got its idea, it also gave me some inspire.
its code like :
if (callback_enable)
execution call back

callback_enable is set/clear using registe_callback/
unregister_callback,

hehe, simple coding,complex concept.

I think vmm is more suitable for unit test,
doest fit big design, for it can not avoid compile time when
trunaround testcase. teal have parameter maybe can avoid trunaroud
time.

also I would like see vmm to opensource like teal/avm.

actually I always prefer c++ and systemC, for c++ have so many
opensource package, if everyone know c++ well, I dont see any market
to systemverilog. when talk with others, nobody support my idea, :-(,I
am sure this is also cadence's advance verification methodology idea.
so,systemC ,ius support better than vcs, ius support mix verilog/
systemC in any hierarchy to support it "advance verification
methodology", but this is lacked in vcs.

teal/truss have the same user interface between c++/systemC/
systemverilog, right? if yes this is a big outcoming.now vmm only in
systemVerilog.
I will use teal/vmm in my next verification task.

vcs is not "golden standard", I always call it a xxx for its obviously
bugs.

here I have a question, how do see class property in waveform?
I always display it. EDA vendor is so silent for this requirement in
their document.

sorry for any words that are not accurate.

Best Regards,
maxwell
Click to expand...
 
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