Systemverilog synthesizable Parameterized interfaces with mo

[vijay]

I have an interface declaration as below
interface i #(parameter width=4);
logic [width:0] a;
modport out (output a);
modport in ( input a);
endinterface
//Now I want to create a module as follows
module b ( i#(.width(10)).in x, i#(.width(20)).out y);
assign y.a=x.a;
endmodule;

Compiling this with dc results in the following error message
test.sv:7: Syntax error at or near token '#'.

Any insight on what I am doing wrong and how to resolve this?
Regards
Vijay

 

[Jonathan Bromley]

On Tue, 14 Dec 2010 20:07:49 -0800 (PST), vijay wrote:

I have an interface declaration as below
interface i #(parameter width=4);
logic [width:0] a;
modport out (output a);
modport in ( input a);
endinterface
//Now I want to create a module as follows
module b ( i#(.width(10)).in x, i#(.width(20)).out y);
assign y.a=x.a;
endmodule;

Compiling this with dc results in the following error message
test.sv:7: Syntax error at or near token '#'.

Any insight on what I am doing wrong and how to resolve this?

I don't think the language spec allows this.

You could try using a generic interface specification on
the ports:

module b (interface.in x, interface.out y);

and now you can hook the ports to any interface that has
modports "in" and "out", regardless of name or parameterization.
Of course it's now your responsibility to check that the actual
connected interface is appropriate, otherwise you'll get some
very strange error messages at elaboration time (or, worse,
very strange behaviour at runtime).

Interfaces really don't mix with any attempt to be rigorous
about data type. But that's a battle I almost certainly
have lost...
--
Jonathan Bromley