SystemVerilog sscanf exasperation

  • Thread starter Jonathan Bromley
  • Start date
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Jonathan Bromley

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OK, so SystemVerilog is hyper-cool and object-oriented and stuff.
So here's me trying to read in some text and decide what kind of
value that text represents - so, for example, I'd like to be able
to read the text
100
and decide that it's an integer,
-34.5e4
and decide it's a real,
supercalifragilisticexpialidocious
and decide it's a string. And maybe other types, later.

Now I've been at this game a while, so I'm quite capable of
writing number-reading software for myself. But it seems to me
that those nice folk at the sim vendors already did that for me, and
gave me $sscanf. So I try to use that. I've got my string in a
string variable "str", and I would like to see if I have an integer.
(More types to do later, but that's a start.) Here's my effort:

int count, val;
string str, junk;
...
str = <whatever>;
count = $sscanf(str, "%d%s", val, junk);

At this point I expect count==0 if my string was nothing like
an integer. I expect count==1 if there's an integer and nothing
else (except possibly whitespace) in the string. And I expect
count==2 if there's an integer followed by something I don't want.
So let's try it with the latest offerings from three vendors.

One of 'em doesn't support strings yet. I'll try it again later
with a plain-old Verilog-style string (yuk!), but meanwhile...

The other two, given a simple integer like "256", both give
count==1 and fill up my "val" variable as expected. Good.

So, let's try some error cases - a foolish thing to do, I know,
but hey, let's live a little. For a string containing a single
uppercase A,
- vendor X gives me count==1, val==65 :)
- vendor Y gives me count==0 (CORRECT!! Hurrah!!)
(Even more bizarre: for the string "AA", vendor X gives
val==16705. Go figure.)

For the string "4'b11" (without its enclosing quotes),
- vendor X gives me count==2, val==4, junk=="'b11" (Yippee!)
- vendor Y gives me count==1, val==11 (eh?????)

Finally some good news: for the string "123AAA", both
X and Y give count==2, val==123, junk=="AAA".

Can anyone comment? For me, it's back to the hand-
coded number reader. I hate to say this, because I know
how hard all the vendors have worked to bring SystemVerilog
implementations to market quickly, but surely we
deserve better - $sscanf is not rocket science.

Thanks for letting me get that off my chest :)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Jonathan Bromley wrote:
OK, so SystemVerilog is hyper-cool and object-oriented and stuff.

I hate to say this, because I know
how hard all the vendors have worked to bring SystemVerilog
implementations to market quickly, but surely we
deserve better - $sscanf is not rocket science.
$sscanf was not added in SystemVerilog. It was added in Verilog-2001.
Only your use of the string type is a SystemVerilog extension, and that
is probably unrelated to the bugs you are seeing.

Of course, that just makes your complaint stronger.
 
Jonathon -

I've been playing with Veritak recently, so I thought I'd
try your test cases. Veritak is V-2001, so I needed to
use the old style strings, but....

its $sscanf worked just fine. It returned the proper values
for each test case.

Not a bad simulator for $50! It has some warts, but the
author is VERY speedy about fixing bugs and adding
enhancements.

John Providenza

Jonathan Bromley wrote:
OK, so SystemVerilog is hyper-cool and object-oriented and stuff.
So here's me trying to read in some text and decide what kind of
value that text represents - so, for example, I'd like to be able
to read the text
100
and decide that it's an integer,
-34.5e4
and decide it's a real,
supercalifragilisticexpialidocious
and decide it's a string. And maybe other types, later.

Now I've been at this game a while, so I'm quite capable of
writing number-reading software for myself. But it seems to me
that those nice folk at the sim vendors already did that for me, and
gave me $sscanf. So I try to use that. I've got my string in a
string variable "str", and I would like to see if I have an integer.
(More types to do later, but that's a start.) Here's my effort:

int count, val;
string str, junk;
...
str = <whatever>;
count = $sscanf(str, "%d%s", val, junk);

At this point I expect count==0 if my string was nothing like
an integer. I expect count==1 if there's an integer and nothing
else (except possibly whitespace) in the string. And I expect
count==2 if there's an integer followed by something I don't want.
So let's try it with the latest offerings from three vendors.

One of 'em doesn't support strings yet. I'll try it again later
with a plain-old Verilog-style string (yuk!), but meanwhile...

The other two, given a simple integer like "256", both give
count==1 and fill up my "val" variable as expected. Good.

So, let's try some error cases - a foolish thing to do, I know,
but hey, let's live a little. For a string containing a single
uppercase A,
- vendor X gives me count==1, val==65 :)
- vendor Y gives me count==0 (CORRECT!! Hurrah!!)
(Even more bizarre: for the string "AA", vendor X gives
val==16705. Go figure.)

For the string "4'b11" (without its enclosing quotes),
- vendor X gives me count==2, val==4, junk=="'b11" (Yippee!)
- vendor Y gives me count==1, val==11 (eh?????)

Finally some good news: for the string "123AAA", both
X and Y give count==2, val==123, junk=="AAA".

Can anyone comment? For me, it's back to the hand-
coded number reader. I hate to say this, because I know
how hard all the vendors have worked to bring SystemVerilog
implementations to market quickly, but surely we
deserve better - $sscanf is not rocket science.

Thanks for letting me get that off my chest :)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On 3 Aug 2006 14:48:25 -0700, sharp@cadence.com wrote:

$sscanf was not added in SystemVerilog. It was added in Verilog-2001.
Only your use of the string type is a SystemVerilog extension
Indeed so; but the general clunkiness of strings in Verilog meant
that there was little motivation to do interesting things with them,
whereas the nice shiny new string data type in SV makes text
processing generally a much more productive experience.

[The use of SV strings]
is probably unrelated to the bugs you are seeing.
I agree, hence the comment that I will in due course try
the same thing with reg[]-style strings in the tool that
doesn't yet have SV strings.

Of course, that just makes your complaint stronger.
Well, I'm somewhat regretting making the complaint at all,
since it's a tiny little detail and I really should have reported
it as a bug before moaning here. I *do* report bugs
to vendors, politely and in private; and my experience
is that they are usually very responsive. But I hope
readers (and vendors!) will understand my frustration that
certain vendors seem to have given so little care to the
implementation of certain rather easy things, when they
obviously put so much expertise and effort into the
difficult bits - think about the constraint solver for
SystemVerilog, for example, or coverage data
collection, or assertion processing.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On 3 Aug 2006 16:20:39 -0700, johnp <johnp3+nospam@probo.com> wrote:

I've been playing with Veritak recently
[...]
Not a bad simulator for $50!
Thanks for the pointer - I'll take a look. I wasn't aware of
its existence.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Hi Jonathan,
I am not sure why you state it is an error. It is just a string
conversion to digit? Based on your C knowledge you should be aware the
character "A" is equivalent to 'h41 and when you define "AA", it is
equivalent to 16705 by digit. I play around with this before.

Can't play around now because of license feature issues.

$sscanf is using packaged array string. string is system verilog data
which is dynamic variable. I never try with this with $sscanf.It will
be interesting to figure out the whole details.
I have to wait until end of september for my chances to explore it
again.


Best regards,
ABC

Jonathan Bromley wrote:
OK, so SystemVerilog is hyper-cool and object-oriented and stuff.
So here's me trying to read in some text and decide what kind of
value that text represents - so, for example, I'd like to be able
to read the text
100
and decide that it's an integer,
-34.5e4
and decide it's a real,
supercalifragilisticexpialidocious
and decide it's a string. And maybe other types, later.

Now I've been at this game a while, so I'm quite capable of
writing number-reading software for myself. But it seems to me
that those nice folk at the sim vendors already did that for me, and
gave me $sscanf. So I try to use that. I've got my string in a
string variable "str", and I would like to see if I have an integer.
(More types to do later, but that's a start.) Here's my effort:

int count, val;
string str, junk;
...
str = <whatever>;
count = $sscanf(str, "%d%s", val, junk);

At this point I expect count==0 if my string was nothing like
an integer. I expect count==1 if there's an integer and nothing
else (except possibly whitespace) in the string. And I expect
count==2 if there's an integer followed by something I don't want.
So let's try it with the latest offerings from three vendors.

One of 'em doesn't support strings yet. I'll try it again later
with a plain-old Verilog-style string (yuk!), but meanwhile...

The other two, given a simple integer like "256", both give
count==1 and fill up my "val" variable as expected. Good.

So, let's try some error cases - a foolish thing to do, I know,
but hey, let's live a little. For a string containing a single
uppercase A,
- vendor X gives me count==1, val==65 :)
- vendor Y gives me count==0 (CORRECT!! Hurrah!!)
(Even more bizarre: for the string "AA", vendor X gives
val==16705. Go figure.)

For the string "4'b11" (without its enclosing quotes),
- vendor X gives me count==2, val==4, junk=="'b11" (Yippee!)
- vendor Y gives me count==1, val==11 (eh?????)

Finally some good news: for the string "123AAA", both
X and Y give count==2, val==123, junk=="AAA".

Can anyone comment? For me, it's back to the hand-
coded number reader. I hate to say this, because I know
how hard all the vendors have worked to bring SystemVerilog
implementations to market quickly, but surely we
deserve better - $sscanf is not rocket science.

Thanks for letting me get that off my chest :)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On 4 Aug 2006 08:53:22 -0700, "ABC" <bcang78@gmail.com> wrote:

Hi Jonathan,
I am not sure why you state it is an error.
Because the Verilog LRM says it is.

It is just a string
conversion to digit? Based on your C knowledge you should be aware the
character "A" is equivalent to 'h41 and when you define "AA", it is
equivalent to 16705 by digit.
Indeed so; the behaviour is understandable, but wrong by definition.
I hope you would be very surprised if this were to happen in C's
sscanf() function.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
HI Jonathan,
My understanding is LRM state it is a reg string.What you mean by wrong
by conversion. You are allowed to convert string to decimal and how to
do so without ASCII table? My understanding is LRM never disallowed it.
Is my understanding wrong?


Best regards,
ABC

Jonathan Bromley wrote:
On 4 Aug 2006 08:53:22 -0700, "ABC" <bcang78@gmail.com> wrote:

Hi Jonathan,
I am not sure why you state it is an error.

Because the Verilog LRM says it is.

It is just a string
conversion to digit? Based on your C knowledge you should be aware the
character "A" is equivalent to 'h41 and when you define "AA", it is
equivalent to 16705 by digit.

Indeed so; the behaviour is understandable, but wrong by definition.
I hope you would be very surprised if this were to happen in C's
sscanf() function.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Hi Jonathan,
You can double check LRM and it does show similar conversion as well if
I am not mistaken. Any tools which failed such simple verilog
conversion, I will file bug instead.

Best regards,
ABC

ABC wrote:
HI Jonathan,
My understanding is LRM state it is a reg string.What you mean by wrong
by conversion. You are allowed to convert string to decimal and how to
do so without ASCII table? My understanding is LRM never disallowed it.
Is my understanding wrong?


Best regards,
ABC

Jonathan Bromley wrote:
On 4 Aug 2006 08:53:22 -0700, "ABC" <bcang78@gmail.com> wrote:

Hi Jonathan,
I am not sure why you state it is an error.

Because the Verilog LRM says it is.

It is just a string
conversion to digit? Based on your C knowledge you should be aware the
character "A" is equivalent to 'h41 and when you define "AA", it is
equivalent to 16705 by digit.

Indeed so; the behaviour is understandable, but wrong by definition.
I hope you would be very surprised if this were to happen in C's
sscanf() function.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On 5 Aug 2006 02:37:02 -0700, "ABC" <bcang78@gmail.com> wrote:

Hi Jonathan,
You can double check LRM and it does show similar conversion as well if
I am not mistaken.
I believe you are. Of course the literal "AA", in contexts such as

reg [15:0] R = "AA";

is simply a bit-pattern with the numeric value 16705. But if you read
the documentation for $sscanf in the Verilog-2001 LRM you will
clearly see that its %d "read a decimal integer" conversion is
defined to handle only the digits 0-9, possibly with embedded
underscores and an optional leading sign + or -.

It would be very handy to have a format converter for $sscanf
that accepted the whole Verilog number syntax, including
such things as 4'd5, 16'hFFFF, "AA" and so on. But as far
as I'm aware we do not have such a thing.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Hi Jonathan,
Now, I see your point already. Even with v2k alone it shows same matter
of interest from my site.Thanks. :)

Best regards,
ABC

Jonathan Bromley wrote:
On 5 Aug 2006 02:37:02 -0700, "ABC" <bcang78@gmail.com> wrote:

Hi Jonathan,
You can double check LRM and it does show similar conversion as well if
I am not mistaken.

I believe you are. Of course the literal "AA", in contexts such as

reg [15:0] R = "AA";

is simply a bit-pattern with the numeric value 16705. But if you read
the documentation for $sscanf in the Verilog-2001 LRM you will
clearly see that its %d "read a decimal integer" conversion is
defined to handle only the digits 0-9, possibly with embedded
underscores and an optional leading sign + or -.

It would be very handy to have a format converter for $sscanf
that accepted the whole Verilog number syntax, including
such things as 4'd5, 16'hFFFF, "AA" and so on. But as far
as I'm aware we do not have such a thing.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 

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