Systemverilog: Quartus-II 7.1 and interfaces?

[Altera User]

I've tried using the "interface" construct in a Quartus-II project, but I
can't tell if it's working the way it is supposed to.
I tried declaring an interface like the following:

interface interface_cpu_vgachar_vga(
input logic [15:0] cpu_addr,
input logic cpu_write,
input logic cpu_read,
input logic [15:0] cpu_wdata,
output logic [15:0] cpu_rdata
);
endinterface // : interface_cpu_vgachar_vga

interface interface_cpu_vgachar_cpu(
output logic [15:0] cpu_addr,
output logic cpu_write,
output logic cpu_read,
output logic [15:0] cpu_wdata,
input logic [15:0] cpu_rdata
);
endinterface // : interface_cpu_vgachar_cpu

When I use either interface as a top-level port, Altera's pin-assignment
menu lists them as 'bidir'.
And the synthesis-logfile shows a bunch of warnings like this:
Warning: Inserted an always-enabled tri-state buffer between logic and the
tri-state bus if_cpu.cpu_rdata[0]~15 that it feeds
Warning: The bidir "if_cpu.cpu_wdata[0]" has no source; inserted an always
disabled tri-state buffer.

What am I doing wrong?

 

[Jonathan Bromley]

On Mon, 28 May 2007 11:31:48 -0700, "Altera User"
<altera_user@nospam.com> wrote:

I've tried using the "interface" construct in a Quartus-II project, but I
can't tell if it's working the way it is supposed to.
I tried declaring an interface like the following:

interface interface_cpu_vgachar_vga(
input logic [15:0] cpu_addr,
input logic cpu_write,
input logic cpu_read,
input logic [15:0] cpu_wdata,
output logic [15:0] cpu_rdata
);
endinterface // : interface_cpu_vgachar_vga

OK, but why put everything on ports of the interface?
I suspect you mean something like this...

interface interface_cpu_vgachar_vga;
logic [15:0] cpu_addr;
logic cpu_write;
logic cpu_read;
logic [15:0] cpu_wdata;
logic [15:0] cpu_rdata;
modport peripheral (
input cpu_addr, cpu_write, cpu_read, cpu_wdata,
output cpu_rdata );
endinterface

interface interface_cpu_vgachar_cpu(
output logic [15:0] cpu_addr,

eh? Two different interfaces with the same name?

When I use either interface as a top-level port,

No! You REALLY don't want to do that! Interfaces work well
as internal connections within your design, but it is completely
inappropriate to put interface ports on something that will
appear as the top level. As you have seen, you lose control
over signal directions - and names...

What am I doing wrong?

I *think* you are misunderstanding the concept of "interface".
What you are trying to write is much closer to the concept
of "modport". But even modports cannot be used as ports on
your top level design.
--
Jonathan Bromley, Consultant

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