SystemVerilog -- pros and cons

[Mark Brehob]

Hello all,
I teach a class where the students spend some 200 hours coding a large
project in Verilog. We do simulation and synthesis (using design
compiler) but don't do layout etc. I've got a group of students
asking to use SystemVerilog. My questions:
- This looks like more of an upgrade (like Verilog 2001/2005) then a
different language. Is that accurate?
- Is there anything I need to worry about with respect to design
compiler and synthesis?
- Is there a good tutorial for Verilog users to learn SystemVerilog?
I've found some talks/overviews but no real tutorials.
- Is there anything I should be worried about that the above
questions didn't cover?

Thanks,
Mark

 

[Jonathan Bromley]

Mark

I teach a class where the students spend some 200 hours coding a large
project in Verilog.  We do simulation and synthesis (using design
compiler) but don't do layout etc.  I've got a group of students
asking to use SystemVerilog.  My questions:

 - This looks like more of an upgrade (like Verilog 2001/2005) then a
different language.  Is that accurate?

Strictly speaking, yes. It's built on top of, and is in almost every
respect backward compatible with, 1364-2005 Verilog. However, it's
a bit like asking whether a car is an upgrade from a handcart - they
both have four wheels, can run on roads and can carry stuff.....
There is SO MUCH new stuff in SV that it almost feels like a new
language. That's particularly true of the assertions and
OOP extensions.

 - Is there anything I need to worry about with respect to design
compiler and synthesis?

DC has excellent support for pretty much the whole synthesizable
subset of SV. Interfaces, unique/priority conditionals, always_???,
shorthand port connections using .* - all these things are fully
supported by DC. Of course, there is a ton of verification-only
stuff in SV that is never likely to be synthesizable - dynamic and
associative arrays, classes, clocking blocks and so forth.

 - Is there a good tutorial for Verilog users to learn SystemVerilog?
I've found some talks/overviews but no real tutorials.

Yeah, our training courses are brilliant Seriously though:
not much. There is some stuff on project-veripage; more usefully
in my opinion, there are some OK textbooks. Try the Sutherland/
Flake/Davidmann book on SV for design, or Chris Spear's book on
SV verification, or Jon Michelson on SV assertions. Trawling
through the recent proceedings of DVCon and DAC may well turn up
some interesting stuff too. Our website www.doulos.com/knowhow
has some assorted resources that you may find useful.

 - Is there anything I should be worried about that the above
questions didn't cover?

Depends on what you want to do. If the focus is synthesizable
design code, no, you're OK. If you care about advanced
verification then you're only scratching the surface; in
particular you need to find out what OVM and VMM are all about
(see www.ovmworld.org and www.vmmcentral.org for more) and you
should be asking about the object-oriented programming features
of SV, and you need to understand coverage-driven constrained
random testing methodology.

One other factoid that may be interesting: Mark Zwolinski of
Southampton University, England has recently shifted from VHDL
to SystemVerilog for some undergraduate classes. Betcha he has
some experience that's highly pertinent to your concerns.

Good luck with the transition, and keep coming back here
if you think there's anything we can do to help.
--
Jonathan Bromley

 

[Jonathan Bromley]

Mark,

An afterthought:

 - Is there a good tutorial for Verilog users to learn SystemVerilog?

There's some interesting stuff on the Resources page
of www.svug.org - I think you may need to register to
get it, but the registration is pain-free and spam-free.
--
Jonathan Bromley

 

[mz]

On 29 Oct, 21:34, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:

One other factoid that may be interesting: Mark Zwolinski of
Southampton University, England has recently shifted from VHDL
to SystemVerilog for some undergraduate classes.  Betcha he has
some experience that's highly pertinent to your concerns.

Hi Jonathon,

Thanks for the plug!


In fact, I've rewritten my VHDL book for SystemVerilog:
http://www.pearsonhighered.com/educator/product/Digital-System-Design-with-SystemVerilog-Safari/9780137046393.page

It should be available in the US *tomorrow* (Nov 2 2009). (The date on
the publisher's web page is wrong.)

Mark Zwolinski

 

[Mark Brehob]

On Nov 1, 11:39 am, mz <mark.zwolin...@gmail.com> wrote:

On 29 Oct, 21:34, Jonathan Bromley <s...@oxfordbromley.plus.com
wrote:

One other factoid that may be interesting: Mark Zwolinski of
Southampton University, England has recently shifted from VHDL
to SystemVerilog for some undergraduate classes.  Betcha he has
some experience that's highly pertinent to your concerns.

Hi Jonathon,

Thanks for the plug!

In fact, I've rewritten my VHDL book for SystemVerilog:http://www.pearsonhighered.com/educator/product/Digital-System-Design...

It should be available in the US *tomorrow* (Nov 2 2009). (The date on
the publisher's web page is wrong.)

Mark Zwolinski

Thanks all, that was really helpful!

I'm going to get a copy of the Sutherland/Flake/Davidmann book. Looks
like I can get a copy cheap.
Mark, it looks like your book didn't make it out quite yet, but I'm
going to request a copy shortly. Not sure it's quite what we are
looking for, but it looks like a course we _should_ have.

Thanks again all, and sorry for the delay in responding. I got
distracted by life.

Mark