Systemverilog property arguments, can I use interface/modpor

I've used interface/modports (in the design RTL) to bundle signal-
groups by functionality, and it synthesizes just fine in Design
Compiler.

Now, I'm trying to write some concurrent SVA assertions at an I/O-
boundary between two functional-blocks.

Unfortunately, I can't seem to declare properties with modport
arguments.
Basically, it seems to me the property-arguments must be 'simple' bit-
signals (logic/reg/wire)

If I try to declare a property with an interface/modport as an
argument, my simulator
(IUS81) quits with a syntax error.

property prop_xyz( clk, rstn, sig );
@( posedge clk ) disable iff (!rstn)
$rose( sig ) |=> $fell( sig ); // 1T pulse-width
endproperty : prop_xyz

//sva_check_sig : assert
property( prop_xyz( .clk(clk), .rstn(rstn), .sig(sig) ) )
sva_check_sig : assert
property( prop_xyz( .clk(clk), .rstn(rstn), .sig(sig) ) )
else $error( "Doh!");

 

On Oct 3, 12:21 pm, wdc.cre...@gmail.com wrote:

I've used interface/modports (in the design RTL) to bundle signal-
groups by functionality, and it synthesizes just fine in Design
Compiler.

Interfaces are not just a bundling mechanism like structs. They are
more like module instances that you can pass around references to.
That affects what you can do with them.

Unfortunately, I can't seem to declare properties with modport
arguments.
Basically, it seems to me the property-arguments must be 'simple' bit-
signals (logic/reg/wire)

They can be other data types. I believe they can be all the same
things that task/function arguments can be, which are all the things
you can declare variables to be. But you cannot declare a variable to
be of type interface. You can pass an interface through a module
port, but not to a task or function.

You can declare a variable to be of type virtual interface, which is
essentially a pointer to an interface. You can assign an interface to
that virtual interface, and then references through that virtual
interface will be references to the assigned interface. Therefore I
assume you could declare a property of type virtual interface and pass
an interface to it. That does not guarantee that your tools will
support it, but I think it would be legal.

Note also that declaring virtual interfaces of particular modport
types or parameterizations was not defined in the 2005 SV standard.
This has been remedied in the next draft revision, but may not be
widely supported.