Systemverilog preprocessor allow "..."?

[Ulsk]

ANSI-C preprocessor supports a 'wildcard' ...
#include<stdio.h>

#define _NOISY_PRINTF( ... ) printf( ... )
#define _QUIET_PRINTF( ... )

int
main( void )
{
_NOISY_PRINTF( "hello world, %d, %d, %d!\n", 1, 2,3 );
// hello world, 1, 2, 3!
//

_QUIET_PRINTF( "hello world, %d, %d, %d!\n", 1, 2,3 );
// <<no output to stdout>>
//
}

I don't suppose Systemverilog's preprocessor supports this?
(And I assume SystemC has no trouble with it...)

 

Ellipsis(...) is a defined stuff in ANSI-C. I doubt if it is so in
SystemVerilog.