SystemVerilog Parameterizable/Generic Interfaces - Ideas?

E

Edmond Coté

Guest
Hello,

What's the status of the following type of interface construct? A
google search revealed that it was discussed in 2004 on the SV-BC list
(http://www.eda.org/sv-bc/hm/1865.html), however, that's the only place
on the web where I've seen any mention.

Example:

interface test_if #(parameter int N = 2);
wire [N-1:0] test;
genvar i;
generate for (i=0; i<N; i++)
modport slave(input test);
endinterface

I am using Mentor Precision RTL and I would like to hear if anyone has
any synthesizable alternatives, short of coding everything out manually
of course.

Thank you,

Edmond Coté
 

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