SystemVerilog Packed Array Assignment

[Shawn Miller]

I'm working on a SystemVerilog package, and I'm trying to define and
initialize a packed array. I'm having an issue using named
concatenation to initialize the array. I'd like to assign each
element of the array explicitly - see example below:

----------------------------------------------------------------------------------
//Type for the configuration of each slave
typedef struct packed {
bit [1:8] [7:0] Name;
logic [23:0] Addr;
} slaveT;

parameter num_slaves = 3;

parameter slaveT [num_slaves-1:0] slave_array = //array of slave
configurations
// Individually define the configuration of each slave
{
0: {Name: "SLV0 ",
Addr: 24'hFE_0000
},

1: {Name: "SLV1 ",
Addr: 24'hFF_0000
},

2: {Name: "SLV2 ",
Addr: 24'hE0_0000
}
};
----------------------------------------------------------------------------------

What I've found is that I can't do this explicit, named concatenation
to a packed array. It works fine with an unpacked array, but it's my
understanding that unpacked structures won't synthesize.
This also works if I remove the explicit element names, and just use a
simple concatenation based on the order of the elements inside the
curly brackets :

----------------------------------------------------------------------------------
parameter slaveT [num_slaves-1:0] slave_array = //array of slave
configurations
// Individually define the configuration of each slave
{
{"SLV0 ",
24'hFE_0000
},

{"SLV1 ",
24'hFF_0000
},

{"SLV2 ",
24'hE0_0000
}
};
----------------------------------------------------------------------------------

My question is, is there any way to do explicit assignment to elements
of a packed array? I'm trying to do this purely for cosmetic reasons,
but it's driving me nuts.

 

[Jonathan Bromley]

On Wed, 12 Aug 2009 12:44:20 -0700 (PDT), Shawn Miller wrote:

I'm working on a SystemVerilog package, and I'm trying to define and
initialize a packed array. I'm having an issue using named
concatenation to initialize the array. I'd like to assign each
element of the array explicitly - see example below:

Whoa! You're getting confused between concatenation
and assignment patterns.

The field naming thing works only when you're in
an assignment pattern using the '{} syntax. Plain
curly brackets {} without the apostrophe give you
a good old-fashioned Verilog concatenation of bits.
See my tiny edits to your code, below (just
adding four apostrophes):

----------------------------------------------------------------------------------
//Type for the configuration of each slave
typedef struct packed {
bit [1:8] [7:0] Name;
logic [23:0] Addr;
} slaveT;

parameter num_slaves = 3;

parameter slaveT [num_slaves-1:0] slave_array =
// Individually define the configuration of each slave
'{
0: '{Name: "SLV0 ",
Addr: 24'hFE_0000
},

1: '{Name: "SLV1 ",
Addr: 24'hFF_0000
},

2: '{Name: "SLV2 ",
Addr: 24'hE0_0000
}
};
----------------------------------------------------------------------------------

Two simulators run this just fine; a third doesn't support
it for assignment to a packed array.

What I've found is that I can't do this explicit, named concatenation
to a packed array. It works fine with an unpacked array

It shouldn't. Your syntax was flat-out wrong, so any tool
that accepts it is non-LRM compliant.

but it's my
understanding that unpacked structures won't synthesize.

I don't see why they shouldn't. It's just that you don't
have a simple one-to-one correspondence between bits in
the unpacked struct and bits in a vector, in the way you
do have with a packed struct.

This also works if I remove the explicit element names, and just use a
simple concatenation based on the order of the elements inside the
curly brackets :

Yes, but that's because you're constructing the whole packed
thing as a simple vector concatenation, and then assigning
it to the packed array of packed structs. This is
exceedingly error-prone; if you get just one field the
wrong length, all bits to the left of that field will be
displaced by the corresponding number of bits. Indeed,
you may have noticed that "SLV0" appears in element[2]
of the array, since your array is numbered [2:0] and "SLV0"
is the leftmost in your concatenation. I guess that
probably wasn't the idea.

My question is, is there any way to do explicit assignment
to elements of a packed array?

Yes, if your tools support it. The two simulators I mentioned,
and Mentor Precision Synthesis, are OK with my version of
your code; I haven't had a chance to try others.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Shawn Miller]

Thanks for the response.
I made the change in my code to use the '{} to match the suggestion
you made:
parameter slaveT [num_slaves-1:0] slave_array =
// Individually define the configuration of each slave
'{
0: '{Name: "SLV0 ",
Addr: 24'hFE_0000
},

1: '{Name: "SLV1 ",
Addr: 24'hFF_0000
},

2: '{Name: "SLV2 ",
Addr: 24'hE0_0000
}
};

This did synthesize just fine with Synplify Pro 2009.06, which was
great. I was confused before - I didn't think you could use the
assignment pattern syntax with packed arrays. This method certainly
is far less error prone.

I did find one thing that doesn't seem quite right, though. When I
changed my vector definition from [2:0] to [0:2], I got different
output from synthesis. I pass these elements one at a time into my
slave module as a parameter:

slave
#(.slv_base_addr (slave_array[0].BaseAddr))
slv (
...
)

When my array is defined [0:2], this works fine. When I define it as
[2:0], slave_array[0].BaseAddr is 24'hE0_0000, which should have been
slave_array[2].BaseAddr. The parameters were assigned to the slaves
in reverse order. I would expect that since I'm explicitly assigning
elements of the vector, and explicitly passing in one element at a
time to my slave module, how I define the direction wouldn't matter.
Is that what you would expect? I'm going to follow up with my
Synplicity AE on this.

Thanks,
shawn