Systemverilog, Modelsim/Questasim, and clocking blocks

[jlivermore]

I have been trying several example designs in Questasim 6.2c that do
not seem to be able to trigger off of a clocking block event through a
virtual interface. The release notes say that 6.2 supports virtual
interfaces with clocking blocks.

Execution seems to get stuck when it gets to this kind of statement:
@s.sb;
as seen in the drive task below.

Anyone else see this? Is this a Modelsim/Questasim issue? I would
think execution would continue after the next rising clk (well, two
clocks since there is a repeat(2) statement.) But it never resumes.

Jason

-----------

Example code snippets:

interface A_Bus(input bit clk);
wire req, gnt;
wire [7:0] addr, data;

clocking sb @(posedge clk);
input gnt;
output req, addr;
inout data;
endclocking

modport DUT (....);

modport STB (clocking sb);
endinterface

module dev1(A_Bus.DUT b);
....
endmodule

program T(A_Bus.STB b1);

typedef virtual A_Bus.STB SYNCTB;

task request(SYNCTB s);
...

task wait_grant(SYNCTB s);
...

task drive(SYNCTB s, logic[7:0] adr, data);
if(s.sb.gnt == 0) begin
request(s);
wait_grant(s);
end
s.sb.addr = adr;
s.sb.data = data;
repeat(2) @s.sb;
s.sb.req = 0;
endtask

initial begin
drive(b1, $random, $random);
end
endprogram

module top5;
bit clk;

always
begin
#5 clk = ~clk;
end

A_Bus b1(clk);

dev1 d1(b1);

T tb(b1);
endmodule