J
Jonathan Bromley
Guest
Any SystemVerilog gurus out there???
Three problems from the SystemVerilog 3.1 LRM (Accellera)
for your delectation and amusement... and if anyone
can help me understand the details, I'd be most grateful.
1) Is there any difference between "logic" and "reg"?
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
I know there was lots of discussion about this when it
was being developed, but now the LRM speaks with more than
one voice.
LRM table 3-1:
logic: [a data type like reg] with different
use rules from reg
LRM section 5.1 paragraph 4:
the keyword logic is added as a more accurate
description that is equivalent to reg
2) You can't have variables as inout ports... or can you?
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
If you really must attach a variable to an inout port,
the right way to do it is by using ref ports. However,
the LRM creates FUD thus:
BNF syntax:
inout_declaration ::=
inout [ port_type ] list_of_port_identifiers
| inout data_type list_of_variable_identifiers
LRM section 18.8.1:
A variable data type is not permitted on either
side of an inout port.
3) Interpreters required
~~~~~~~~~~~~~~~~~~~~~~~~
Can someone please explain WTF this means? In particular,
on what planet does a data TYPE ever WRITE anything?
LRM section 5.6:
All data types can write through a port.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Three problems from the SystemVerilog 3.1 LRM (Accellera)
for your delectation and amusement... and if anyone
can help me understand the details, I'd be most grateful.
1) Is there any difference between "logic" and "reg"?
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
I know there was lots of discussion about this when it
was being developed, but now the LRM speaks with more than
one voice.
LRM table 3-1:
logic: [a data type like reg] with different
use rules from reg
LRM section 5.1 paragraph 4:
the keyword logic is added as a more accurate
description that is equivalent to reg
2) You can't have variables as inout ports... or can you?
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
If you really must attach a variable to an inout port,
the right way to do it is by using ref ports. However,
the LRM creates FUD thus:
BNF syntax:
inout_declaration ::=
inout [ port_type ] list_of_port_identifiers
| inout data_type list_of_variable_identifiers
LRM section 18.8.1:
A variable data type is not permitted on either
side of an inout port.
3) Interpreters required
~~~~~~~~~~~~~~~~~~~~~~~~
Can someone please explain WTF this means? In particular,
on what planet does a data TYPE ever WRITE anything?
LRM section 5.6:
All data types can write through a port.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.