SystemVerilog: "logic" or "ulogic?"

[Cliff Cummings]

Hi, All -

Request for user feedback.

Two data types have been added to the SystemVerilog language: "logic"
and "bit."

The new types are actually unresolved types (similar to the VHDL
std_ulogic_type) and are called "logic" (4-state type) and "bit"
(2-state type).

I believe we would be doing the Verilog and VHDL communities a favor
by at least choosing the more VHDL-like keywords: ulogic & ubit.

I am also guessing that "ulogic" will kill fewer existing designs than
"logic" (same argument for "ubit" vs. "bit"). I also like the
VHDL-like "u" to indicate "unresolved."

Unfortunately, the Accellera SystemVerilog committees are mostly
staffed by EDA vendors who do not want to change the keywords as they
are currently defined in the SystemVerilog 3.0 & 3.1 standards.

I have been given the chance to solicit user input one more time
before this issue is dismissed.

If you have an opinion one way or the other, please send an email
message to the:

SystemVerilog Design Committee ( sv-bc@eda.org )
with the Subject: logic -vs- ulogic - user input

And voice your opinion that either "logic" and "bit" should keep the
current keywords, or
"logic" and "bit" should be changed to the more VHDL-compatible names
of "ulogic" and "ubit."

I really would like more user feedback before we cast this in stone in
SystemVerilog.

Thanks in advance to anyone who responds.

Regards - Cliff Cummings

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
Verilog On-Site Training Sale - 4-day Courses for $1,200/Student
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training

 

[Uncle Noah]

cliffc@sunburst-design.com (Cliff Cummings) wrote in message news:<7788812d.0309161046.42fceefb@posting.google.com>...

Hi, All -

Request for user feedback.

Two data types have been added to the SystemVerilog language: "logic"
and "bit."
I believe we would be doing the Verilog and VHDL communities a favor
by at least choosing the more VHDL-like keywords: ulogic & ubit.

Personally i think if you are going to do a rip-off of VHDL, then you
have to do it right. I like having resolved signals so not to bother
or in extreme case to be able to write my own resolution functions if
i want to (for simulation).

ubit and ulogic are good idea for us to help in designing working bus
architectures.

*Now* is the right time, since SystemVerilog has not stabilized as
IEEE standard yet.

Uncle "The G.B. Man"