SystemVerilog is extend to verilog?

[Nasrin Eshraghi]

Hello,

I need to know System Verilog is extension Verilog? if yes would you give me extensions?
I want to add SystemVerilog to a tool which synthesizing Verilog code for FPGA. I am not sure SystemVerilog is fit to my work.

Many thanks,
Nasri

 

[Y.V.V.Nagendra]

Hello!

SystemVerilog is an extension of Verilog. It's true.

But it's "not" like a new update from android, which u just need to download and install so that new version will be running in ur device (Phone).

It's a conceptual extension. I mean, all the features of verilog are included in SystemVerilog, and few more features newly added to facilitate better abstraction levels for verification.

So adding a package to ur simulator, which only supports Verilog (like Xilinx ISE), doesn't make it compatible to SystemVerilog. For that you need to get a simulator which specifies that it supports SystemVerilog.

Hope I'm clear with my point.

Regards.

 

[Nasrin Eshraghi]

On Tuesday, October 2, 2018 at 9:16:58 AM UTC-3, Y.V.V.Nagendra wrote:

Hello!

SystemVerilog is an extension of Verilog. It's true.

But it's "not" like a new update from android, which u just need to download and install so that new version will be running in ur device (Phone).

It's a conceptual extension. I mean, all the features of verilog are included in SystemVerilog, and few more features newly added to facilitate better abstraction levels for verification.

So adding a package to ur simulator, which only supports Verilog (like Xilinx ISE), doesn't make it compatible to SystemVerilog. For that you need to get a simulator which specifies that it supports SystemVerilog.

Hope I'm clear with my point.

Regards.

Thank you so much,
I got it ,But one thing I want to know is that Verilog and SystemVerilog are like C and C++? for compiling C++ code, do not need C++ compiler, it needs C++ preprocessor and C compiler. I want to know is it possible to add SystemVerilog to my simulation!
I really appriciate

 

[Y.V.V.Nagendra]

Verilog and SystemVerilog are not like C and C++.
Verilog is developed from C and SystemVerilog developed from C,C++ and few other languages.

 

[dsc]

If you want to add design elements of system Verilog to your simulation, most simulators handle it, usually with a compile switch like -sv. But if you are referring to the advanced verification features of SV, likely not unless you have the license and tool to handle it. (The language has features that are synthesizable and other features just for verification. Generally I’ve seen the synthesizable features also supported for simulation nowadays)