Systemverilog interfaces

V

Verictor

Guest
I wonder if anyone here had seen this before: I have a datapath that
communicates between Systemverilog and Matlab, in which DPI-C and
Matlab engine have been used. The engine has been tested in C/Matlab
and works correctly. However, it is funny that when combining SV/C/
Matlab together, the Matlab function only exectues one line. For
example, a Matlab function like

function result = foo(in)
result = 2* in;
end

will work and SV gets correct result. If the function becomes this:

function result = foo(in)
temp = 2 * in;
result = temp + 5;
end

Then SV won't get correct result (result always 0 regardless what
value of in). Tracing Matlab engine variables, and it seems all
variables passing from SV are correct.

Matlab version is 2007a and gcc is 4.1.2.

Thanks.
 

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