SystemVerilog Interfaces: how to share an interface defintio

[Andrew FPGA]

Hi,
I'm trying to use the SystemVerilog interface construct to connect my
class based testbench environment to the instantiation of the device
under test. As I understand it, this is a classic use of the SV
interface construct, since I have seen several examples in Chris
Spears SV for verification book and read the Jonathon Bromley/mentor
graphics paper discussing some of the problems with SV interfaces. My
problem is, the examples in Chris Spears book are simplified to the
point where the scoping issues are unclear.

Where/how do I define the dut interfaces in such a way that they can
be shared(used) by the module instantiating the dut and in my class
based testbench environment?

My first attempt was to define the interfaces inside a package, and
then import the package into the module instantiating the dut, and
importing the package into a driver class that drives the dut pins. Of
course this is illegal, since interfaces cannot be defined inside a
package, they can only be defined inside a compilation unit, module,
or another interface.

Presumably I need to define the interfaces in a compilation unit (i.e.
a file). But then how do I include this in other files? If defined
like this, do they have global scope? Maybe this question has nothing
to do with interfaces - it might be I just dont understand SV
compilation units and scoping issues properly yet. I also have a
problem where I define a class in one file, then in another file I try
to declare and construct an object of that class, but it errors saying
its an unknown type....

I'm an experienced VHDL guy, learning SV for the first time. Modelsim
Questa 6.3. The dut is VHDL.

Regards
Andrew

 

[Amal]

On Aug 5, 2:27 am, Andrew FPGA <andrew.newsgr...@gmail.com> wrote:

Hi,
I'm trying to use the SystemVerilog interface construct to connect my
class based testbench environment to the instantiation of the device
under test. As I understand it, this is a classic use of the SV
interface construct, since I have seen several examples in Chris
Spears SV for verification book and read the Jonathon Bromley/mentor
graphics paper discussing some of the problems with SV interfaces. My
problem is, the examples in Chris Spears book are simplified to the
point where the scoping issues are unclear.

Where/how do I define the dut interfaces in such a way that they can
be shared(used) by the module instantiating the dut and in my class
based testbench environment?

My first attempt was to define the interfaces inside a package, and
then import the package into the module instantiating the dut, and
importing the package into a driver class that drives the dut pins. Of
course this is illegal, since interfaces cannot be defined inside a
package, they can only be defined inside a compilation unit, module,
or another interface.

Presumably I need to define the interfaces in a compilation unit (i.e.
a file). But then how do I include this in other files? If defined
like this, do they have global scope? Maybe this question has nothing
to do with interfaces - it might be I just dont understand SV
compilation units and scoping issues properly yet. I also have a
problem where I define a class in one file, then in another file I try
to declare and construct an object of that class, but it errors saying
its an unknown type....

I'm an experienced VHDL guy, learning SV for the first time. Modelsim
Questa 6.3. The dut is VHDL.

Regards
Andrew

Have you looked at different class libraries for SV? OVM and VMM are
very popular and they have examples of doing this.

http://www.ovmworld.org/
http://www.vmmcentral.org/

Interface is like any other module that you instantiate in another
module. One common way that OVM uses is to define an interface,
instantiate it in a module. At the same time create an instance of
your class-based test-bench. In your class-based test-bench where you
want to access an interface, you declare a virtual interface that is
similar to a pointer to an interface. You need to assign a (concrete)
instance of an interface to this virtual interface somehow. Once that
is done, you class-based test-bench can access signals in the
interface. There are other possibilities as well.

-- Amal

 

On Aug 5, 2:27 am, Andrew FPGA <andrew.newsgr...@gmail.com> wrote:

Where/how do I define the dut interfaces in such a way that they can
be shared(used) by the module instantiating the dut and in my class
based testbench environment?

Interfaces are like modules in this respect. Assuming that you don't
define them nested inside another module or interface, they are global
across the entire design.

Presumably I need to define the interfaces in a compilation unit (i.e.
a file). But then how do I include this in other files? If defined
like this, do they have global scope? Maybe this question has nothing
to do with interfaces - it might be I just dont understand SV
compilation units and scoping issues properly yet.

Module/interface names are not in the compilation unit name space,
they are in the definitions name space. Modules pre-date compilation
units in the language, and have always been global.

I also have a
problem where I define a class in one file, then in another file I try
to declare and construct an object of that class, but it errors saying
its an unknown type....

Here you are presumably dealing with compilation unit scope issues.

I would suggest that you stop trying to use compilation unit scopes,
which create a variety of problems. Packages are much cleaner, and
you should be comfortable with them as a VHDL guy.

Modules/interfaces may look like they are in the compilation unit
scope, but they aren't really. They are global (though there are some
rules about duplicate names that involve the compilation unit scope).

 

[Andrew]

Ok, thanks guys.
Now defining my class in a package and importing it.

The global namespace for the interface definitions was a bit of a
surprise. But if thats the way it is, that is the way it is.

Yes I'm using virtual interfaces. Seems to work well.

Cheers
Andrew

 

On Aug 6, 12:28 am, Andrew <andrew.brid...@gmail.com> wrote:

Now defining my class in a package and importing it.

That will be easier to control and understand.

The global namespace for the interface definitions was a bit of a
surprise. But if thats the way it is, that is the way it is.

Interfaces are mostly a special case of modules, and follow the same
rules where applicable. SV has to be backward compatible with
Verilog, and a global module namespace pre-dates the addition of
compilation units in SV by a couple of decades.