SystemVerilog interfaces and modports, can't drive an input?

[mrfirmware]

I've written my testbench in SV to verify a Verilog RTL design. There
is a simple bus that I use to communicate with the design. The design
drives the clock for this bus. I've written an interface for my side
(testbench) to keep things neat. In my "null modem" module, I cross-
wire the designs bus signals to my testbench's bus signals. However,
my tool is complaining that I cannot drive a modport input with the
design's output signal. I can't figure out what I'm doing wrong.
Here's a simple demo of my problem.

interface bus_if;
logic clock;
modport mst (output clock);
modport slv(input clock);
endinterface

module verilog_rtl;
reg clock; /* not module output for various reasons */
/* drive clock at some freq */
endmodule

module sv_tb(bus_if.slv bus);
assign bus.clock = verilog_rtl.clock;
/* use design's clock as bus.clock now */
endmodule : sv_tb

module sv_top;
bus_if bus();

sv_tb tb(bus);
verilog_rtl rtl();
endmodule : sv_top

The tools says something to the effect of modport port cannot be
driven, port "clock" of modport "slv" has been restricted as input
port. Input ports cannot be driven. However, I think my tb is slaving
off the design's clock so I figured I should use the slv modport. What
don't I get here?

Thanks,

- Mark

 

[humann]

On Oct 24, 1:31 pm, mrfirmware <mrfirmw...@gmail.com> wrote:

I've written my testbench in SV to verify a Verilog RTL design. There
is a simple bus that I use to communicate with the design. The design
drives the clock for this bus. I've written an interface for my side
(testbench) to keep things neat. In my "null modem" module, I cross-
wire the designs bus signals to my testbench's bus signals. However,
my tool is complaining that I cannot drive a modport input with the
design's output signal. I can't figure out what I'm doing wrong.
Here's a simple demo of my problem.

interface bus_if;
logic clock;
modport mst (output clock);
modport slv(input clock);
endinterface

module verilog_rtl;
reg clock;  /* not module output for various reasons */
/* drive clock at some freq */
endmodule

module sv_tb(bus_if.slv bus);
assign bus.clock = verilog_rtl.clock;
/* use design's clock as bus.clock now */
endmodule : sv_tb

module sv_top;
bus_if bus();

sv_tb tb(bus);
verilog_rtl rtl();
endmodule : sv_top

The tools says something to the effect of modport port cannot be
driven, port "clock" of modport "slv" has been restricted as input
port. Input ports cannot be driven. However, I think my tb is slaving
off the design's clock so I figured I should use the slv modport. What
don't I get here?

Thanks,

- Mark

In modport slv, you declare clock as input, which you can't drive.
// you code
modport slv(input clock); // declare clock as input
...
assign bus.clock = verilog_rtl.clock; // drive an input ??!!


I change your code to

assign verilog_rtl.clock =bus.clock;

and compile it with VCS(A-2008.09) without any problems.

Best regards

Hongqing Hu
Verification Engineer
PACT XPP Technologies AG