A
Andrew Burnside
Guest
Hi
I am using SystemVerilog for a mixture of synthesis and testbench work
for a FPGA design. The interface definition is at the bottom of this
post.
I have a common bus that runs down through multiple design blocks.
This is broken out through muxes in some intermediate modules, rather
than having mux logic in the interface itself.
A <-i/f-> B <-i/f-> C etc.
This works absolutely fine for synthesis - I have a `ifdef SIMULATION
option which takes out clocking blocks
However, I am suffering a problem when trying to using this interface
as a testbench, due to both continuous (normal usage) and procedural
(clocking block) assignments to the same signals.
Ideally, I would like to have an interface that will function in both
modes, as then the test stimulus can be the same for both module test
and integration test.
Does anyone know if this is possible, or is it necessary to have a
special test version of the interface, that is specially included at
the top level?
The problem here being Testbench <-i/f-> A would want the clocking
block version of the interface and A <-i/f-> B would want a continous
assignment version.
Does anyone have thoughts on this?
Cheers
Andrew
P.S. The reason I have the clock as a separate port, is so that in the
testbench version I can pass the clock across to the program block
separately, to skew signals that aren't in the interface clocking
block.
------
//Interface def
`ifndef DATA_H
`define DATA_H
`timescale 1ns/10ps
`define SIMULATION
`ifdef SIMULATION
interface DATABUSINTERFACE(input logic clk);
`else
interface DATABUSINTERFACE;
logic clk;
`endif
//allow clock as an input, when using in testbench
logic wren;
logic rden;
logic [31:0] data_in; //split tristate bus at a higher level to
simplify lower blocks
logic [31:0] data_out;
`ifdef SIMULATION
//Clocking block for test signals
clocking cb @(posedge clk);
default input #1ns output #1ns;
output wren;
output rden;
output data_in;
input data_out;
endclocking
modport Test(clocking cb);
`endif
modport Master
(output clk,
output wren,
output rden,
output data_in,
input data_out
);
modport Slave
(input clk,
input wren,
input rden,
input data_in,
output data_out
);
endinterface : DATABUSINTERFACE
`endif
I am using SystemVerilog for a mixture of synthesis and testbench work
for a FPGA design. The interface definition is at the bottom of this
post.
I have a common bus that runs down through multiple design blocks.
This is broken out through muxes in some intermediate modules, rather
than having mux logic in the interface itself.
A <-i/f-> B <-i/f-> C etc.
This works absolutely fine for synthesis - I have a `ifdef SIMULATION
option which takes out clocking blocks
However, I am suffering a problem when trying to using this interface
as a testbench, due to both continuous (normal usage) and procedural
(clocking block) assignments to the same signals.
Ideally, I would like to have an interface that will function in both
modes, as then the test stimulus can be the same for both module test
and integration test.
Does anyone know if this is possible, or is it necessary to have a
special test version of the interface, that is specially included at
the top level?
The problem here being Testbench <-i/f-> A would want the clocking
block version of the interface and A <-i/f-> B would want a continous
assignment version.
Does anyone have thoughts on this?
Cheers
Andrew
P.S. The reason I have the clock as a separate port, is so that in the
testbench version I can pass the clock across to the program block
separately, to skew signals that aren't in the interface clocking
block.
------
//Interface def
`ifndef DATA_H
`define DATA_H
`timescale 1ns/10ps
`define SIMULATION
`ifdef SIMULATION
interface DATABUSINTERFACE(input logic clk);
`else
interface DATABUSINTERFACE;
logic clk;
`endif
//allow clock as an input, when using in testbench
logic wren;
logic rden;
logic [31:0] data_in; //split tristate bus at a higher level to
simplify lower blocks
logic [31:0] data_out;
`ifdef SIMULATION
//Clocking block for test signals
clocking cb @(posedge clk);
default input #1ns output #1ns;
output wren;
output rden;
output data_in;
input data_out;
endclocking
modport Test(clocking cb);
`endif
modport Master
(output clk,
output wren,
output rden,
output data_in,
input data_out
);
modport Slave
(input clk,
input wren,
input rden,
input data_in,
output data_out
);
endinterface : DATABUSINTERFACE
`endif