SystemVerilog - integer range 0 to 9

[Ilya Kalistru]

Hi,
I am learning SV after using VHDL for many years and have a question.

In VHDL I often declare signals this way:
signal cntr : natural range 0 to MaxCntrValue;
This allows me not to worry about number of bit in cntr, while I am sure that a synthesizer will use minimal sufficient number of them for the signal.

Is there a way in SV to make this trick? May be it can be done through a new type declaration or other way...

Or should I always use bit vectors with implicit declaration of number of bit in them?

 

[Kevin Neilson]

Is there a way in SV to make this trick? May be it can be done through a new type declaration or other way...

Or should I always use bit vectors with implicit declaration of number of bit in them?

This is how it's typically done:

parameter CNT_MODULO = 10; // Counts 0..9
reg [$clog2(CNT_MODULO)-1:0] cntr;

 

[Gabor]

On Tuesday, 5/9/2017 6:16 PM, Kevin Neilson wrote:

Is there a way in SV to make this trick? May be it can be done through a new type declaration or other way...

Or should I always use bit vectors with implicit declaration of number of bit in them?

This is how it's typically done:

parameter CNT_MODULO = 10; // Counts 0..9
reg [$clog2(CNT_MODULO)-1:0] cntr;

I don't know if Xilinx finally fixed this in the latest Vivado,
but they have had problems with using $clog2 in declarations.
Strangely if you write your own function for it (Xilinx even
provided one in an answer record) it synthesizes with no problem.
I don't remember whether Vivado had the problem with the reg
declaration as above, but I know that if instead you first try
to set a parameter using $clog2 you'd get an error. For example:

parameter CNT_MODULO = 10; // Counts 0..9
localparam CNT_MODULO_BITS = $clog2(CNT_MODULO);
reg [CNT_MODULO_BITS-1:0] cntr;

would give an error in the second line during synthesis.

--
Gabor

 

[unfrostedpoptart]

On Tuesday, May 9, 2017 at 3:16:08 PM UTC-7, Kevin Neilson wrote:

Is there a way in SV to make this trick? May be it can be done through a new type declaration or other
parameter CNT_MODULO = 10; // Counts 0..9
reg [$clog2(CNT_MODULO)-1:0] cntr;

FYI, if you're going from VHDL to SV, you should use "logic", not "reg".

 

[Ilya Kalistru]

Kevin Neilson, Gabor, unfrostedpoptart thank you for your responses.

This is basically the way I do on VHDL when I want to use a vector instead of integer, for some reason.

 

[Kevin Neilson]

On Saturday, May 13, 2017 at 2:26:25 PM UTC-6, Ilya Kalistru wrote:

Kevin Neilson, Gabor, unfrostedpoptart thank you for your responses.

This is basically the way I do on VHDL when I want to use a vector instead of integer, for some reason.

It's all the same in Verilog. You can use the "integer" keyword, but I believe "integer" and "reg signed [31:0]" are identical.

If the code is written in a straightforward way, the synthesizer will usually detect any surplus bits that are never used and prune them away. (Synplify does this; I assume others do.)

 

[rickman]

On 5/13/2017 4:41 PM, Kevin Neilson wrote:

On Saturday, May 13, 2017 at 2:26:25 PM UTC-6, Ilya Kalistru wrote:
Kevin Neilson, Gabor, unfrostedpoptart thank you for your responses.

This is basically the way I do on VHDL when I want to use a vector instead of integer, for some reason.

It's all the same in Verilog. You can use the "integer" keyword, but I believe "integer" and "reg signed [31:0]" are identical.

If the code is written in a straightforward way, the synthesizer will usually detect any surplus bits that are never used and prune them away. (Synplify does this; I assume others do.)

One of my gripes with synthesis engines is that they do this and report
it in warnings. When writing software I want my code to be error and
warning free. But even if I code to the bit level, there are constructs
added by the synthesis engine that are part of some macro which are
optimized away. An example is counters. The macros used in synthesis
have carries out. If they aren't used the tool reports that as an
output to be optimized away in a warning. So I end up with a list of
warnings I have to verify against before releasing any iteration of the
design for testing. What a PITA. I suppose if I wanted to spend some
time with it I could write a script that processed the report for any
mismatches in the warnings.

Maybe this is overkill, but that is the way I code in C (not that I do
that anymore) and it has proven valuable at times.

--

Rick C