SystemVerilog: Initialization at declaration, okay or discou

[mrfirmware]

(Disclaimer: I ask this question only as it pertains to testbench
code.)

I seem to remember someone saying some time ago that it is potentially
dangerous to initialize a variable at declaration time, e.g.

if (cond) begin : named_block
some_type var_name = SOME_INIT_VAL;
...
end


So I've been doing a lot of this:

if (cond) begin : named_block
some_type var_name;
var_name = SOME_INIT_VAL;
...
end


Which wastes vertical space making it harder to keep it "all on
screen" when there are many variable declarations followed by
assignments.

My question is, do I need to do this? Is it completely safe and
correct to provide an initial value at declaration time? What if I
initialize with the return value of a function call? We do this in C
(my background for the last 19 years) all the time.

Thanks,

- Mark

 

On Jan 18, 11:12 am, mrfirmware <mrfirmw...@gmail.com> wrote:

I seem to remember someone saying some time ago that it is potentially
dangerous to initialize a variable at declaration time, e.g.

if (cond) begin : named_block
    some_type var_name = SOME_INIT_VAL;
    ...
end

So I've been doing a lot of this:

if (cond) begin : named_block
    some_type var_name;
    var_name = SOME_INIT_VAL;
    ...
end

My question is, do I need to do this? Is it completely safe and
correct to provide an initial value at declaration time?

The problem is that the initializer does not mean the same thing as
what you have been writing.

Unless it is inside an automatic task/function/module/program, your
variable var_name is a static variable. Even though it is local to
the block, it exists throughout the simulation, and holds its value
between exiting the block and re-entering it again. It only gets
initialized once, at the start of the simulation. It does not get re-
initialized each time the block is entered. Only an automatic
variable would get created and initialized each time the block is
entered.

In C, local variables are automatic by default. You have to
explicitly declare them to be static, which then acts as a reminder
that any initializer will only take effect at the beginning of
simulation. Because Verilog local variables are static by default,
you do not get this explicit reminder.

For this reason, the SV standards committee added a requirement that
local static variables could only have initializers if they were
explicitly declared to be static. Otherwise the user would get an
error. The user would have to add the "static" keyword to provide
clear documentation of the expected behavior. More likely, they would
realize that this static variable would not have the behavior they
expected, and either make it automatic or use the workaround that you
have been using. Unfortunately, a subcommittee that was not in charge
of this part of the standard removed this requirement without asking
the subcommittee that was in charge of it. So this requirement is not
part of the current standard. There has been an attempt to reinstate
it, which has met resistance on the basis that it would not be
backward compatible now.

What if I
initialize with the return value of a function call? We do this in C
(my background for the last 19 years) all the time.

It is legal. Verilog required initializers to be constant
expressions, but SystemVerilog does not. Note that this could lead to
indeterminate behavior if one initializer depends on another
initialized variable, since the order of execution of initializers is
not specified.

 

Thank you for the detailed answer.
May I know how can I get access to current patches or updates given by researchers to System Verilog?