systemverilog - how to use sv_seed with Questasim of mentor

[gure]

hi,
I wouldlike to run a test several times, each time with different seed.
I don't want each time to choose a specific seed, i would like to use
random seed. What is the easiest way to do so?

 

[Swapnajit Mittra]

Use system date:

<URL:
http://groups.google.com/group/comp.lang.verilog/browse_frm/thread/9ad62c9c0a9905ef/9603cd82dc323ae0?q=amtime1970&rnum=1#9603cd82dc323ae0>

Or, std::randomize() of SystemVerilog.
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