A
Andrew FPGA
Guest
Hi SV and verilog folk,
I would like to specify an array range using a constant, for code
readability, etc reasons. Yet, the obvious results in a Questa 6.6
compile error. Surely SV supports such a basic thing as this somehow?
Any ideas on how I can do this?
e.g.
//declare a constant like this.
const uint8 NUM_1G_PORTS = 4;
//attempt to declare an array of objects
GMII_driver GMII_driver_port[0:NUM_1G_PORTS-1]; //line 175
Kaboom, Questa 6.6 chokes on it:
# ** Error: ../../top.sv(175): Range must be bounded by constant
expressions.
Bit frustrating. Been using SV for > 6 months now, using CRV, ABV,
abstract classes, virtual interfaces, mailboxes, queues, etc etc,.
Awesome. But I still can't get something as simple as this to work.
Of course the workaround is to just stick the constant value of 3 in
there. But I resent it deeply
(I suppose I could dynamically allocate...yes this is the best
workaround I have. But can I do it without having to use a dynamic
array, and call new?)
Cheers
Andrew
I would like to specify an array range using a constant, for code
readability, etc reasons. Yet, the obvious results in a Questa 6.6
compile error. Surely SV supports such a basic thing as this somehow?
Any ideas on how I can do this?
e.g.
//declare a constant like this.
const uint8 NUM_1G_PORTS = 4;
//attempt to declare an array of objects
GMII_driver GMII_driver_port[0:NUM_1G_PORTS-1]; //line 175
Kaboom, Questa 6.6 chokes on it:
# ** Error: ../../top.sv(175): Range must be bounded by constant
expressions.
Bit frustrating. Been using SV for > 6 months now, using CRV, ABV,
abstract classes, virtual interfaces, mailboxes, queues, etc etc,.
Awesome. But I still can't get something as simple as this to work.
Of course the workaround is to just stick the constant value of 3 in
there. But I resent it deeply
(I suppose I could dynamically allocate...yes this is the best
workaround I have. But can I do it without having to use a dynamic
array, and call new?)
Cheers
Andrew