A
Andrew
Guest
Hi,
I'm porting a VHDL function to a System Verilog testbench but I can't
see how to port an unconstrained input to SV?
The best I have come up with is to use a dynamic array:
function automatic void lfsr_shift ( bit polynomial[], //polynomial,
e.g. x^4 + x^3 + 1 = 4'b1100
ref bit lfsr_reg
[]); //pass in previous value of lfsr register here, new value
returned here.
But, I then don't know how to do a left shift operation on lfsr_reg.
The following gives an illegal reference to memory error:
lfsr_reg = lfsr_reg << 1;
Variable array indicies do not seem to be supported in SV (rather
surprising?) I.e. the following is not supported - array bounds must
be static.
lfsr_reg = {lfsr_reg[$left(lfsr_reg)-1:$right(lfsr_reg)],
lfsr_feedback};
Any ideas how I can workaround this? As a last resort I can write
loops, but that seems fairly ugly.
Cheers
Andrew
I'm porting a VHDL function to a System Verilog testbench but I can't
see how to port an unconstrained input to SV?
The best I have come up with is to use a dynamic array:
function automatic void lfsr_shift ( bit polynomial[], //polynomial,
e.g. x^4 + x^3 + 1 = 4'b1100
ref bit lfsr_reg
[]); //pass in previous value of lfsr register here, new value
returned here.
But, I then don't know how to do a left shift operation on lfsr_reg.
The following gives an illegal reference to memory error:
lfsr_reg = lfsr_reg << 1;
Variable array indicies do not seem to be supported in SV (rather
surprising?) I.e. the following is not supported - array bounds must
be static.
lfsr_reg = {lfsr_reg[$left(lfsr_reg)-1:$right(lfsr_reg)],
lfsr_feedback};
Any ideas how I can workaround this? As a last resort I can write
loops, but that seems fairly ugly.
Cheers
Andrew