SystemVerilog cross-module reference resolution error

I am developing some testbench code and I am seeing a cross-module
resolution error. Specifically,

Error-[XMRE] Cross-module reference resolution error
Cross module resolution failed. Originating module
'top_level_program'.
"
BfmPhy.sv
", 308: this.cmdTable


cmdTable is an array of 'cmd' objects. The table is declared in a
parent class and is being used in a derived class. When trying to
index into the cmdTable with the following code fragement, I see the
error.
cmdTable(acrtag).copy