SystemVerilog Clocking Block assign data time?

D

Davy

Guest
Hi all,

I use Clocking Block to construct testbench component like driver.
And I am confused with what time Clocking Block to synchronize data.

For example, there is "sync_fifo_if_i" interface instance and
"wr_driver_cb" clocking block.
The clocking block is
//-----
clocking wr_driver_cb @ (posedge clk);
default input #setup_time output #hold_time;
input full,almost_full;
output din,wr;
endclocking : wr_driver_cb
//-----

The data assignment sequence is
//-----
@(sync_fifo_if_i.wr_driver_cb)
din <= data_in;
wr <= 1'b1;
@(sync_fifo_if_i.wr_driver_cb)
//-----

The questions are
1. Will data assignment (synchronize) at the first @... or the second
@...theoretically?
2. Is @(...) din<=data_in; and @(...); din<=data_in; (note the ;
difference in @) difference?

Thanks!
Best regards,
Davy
 
On 5 Dec 2006 03:07:08 -0800, "Davy" <zhushenli@gmail.com> wrote:

Hi all,

I use Clocking Block to construct testbench component like driver.
And I am confused with what time Clocking Block to synchronize data.

For example, there is "sync_fifo_if_i" interface instance and
"wr_driver_cb" clocking block.
The clocking block is
//-----
clocking wr_driver_cb @ (posedge clk);
default input #setup_time output #hold_time;
input full,almost_full;
output din,wr;
endclocking : wr_driver_cb
//-----


The data assignment sequence is
//-----
Click to expand...
PLEASE, PLEASE tell me you are doing this from code running
in a program block. If the following code is running in a module,
then the SV LRM won't help you in deciding what happens. This
loophole will be fixed very soon, but right now it's not well defined.
ALWAYS use program code to access things through a clocking block.

@(sync_fifo_if_i.wr_driver_cb)
Click to expand...
OK, this waits for the next posedge of clk as you expect.

din <= data_in;
Click to expand...
NOOOOO! Don't do that! If you've created a clocking block,
then use it...

sync_fifo_if_i.wr_driver_cb.din <= data_in;

And then your "din" signal will correctly be driven #hold_time after
the clock edge.

The questions are
1. Will data assignment (synchronize) at the first @... or the second
@...theoretically?
Click to expand...
If you do it correctly as I showed, the update to din will take place
#hold_time after the first @.

2. Is @(...) din<=data_in; and @(...); din<=data_in; (note the ;
difference in @) difference?
Click to expand...
No, it's the same except that the semicolon gives you TWO
procedural statements (not one), so you might perhaps need
another begin...end. That's standard Verilog.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Hi Jonathan,

Thanks a lot for the suggestions!

I use sync_fifo_if_i.wr_driver_cb.din <= data_in; in my code. We know
that in program, clocking block assignment will schedule a
reactive-non-blocking-assignment just after #hold_time. And I guess in
module, clocking block assignment will do the same thing. If clocking
block assignment schedule a non-blocking-assignment after
one-clock-cycle plus #hold_time, it will confuse the user.

Because clocking block in Cadence tools always confusing that schedule
a non-blocking-assignment after one-clock-cycle plus #hold_time.
Cadence IUS get different result with Synopsys VCS, which schedule a
reactive-non-blocking-assignment just after #hold_time.

I have drop clocking block and replace it with modport (though I don't
know how to emulate input #setup_time). And modport work OK in Cadence
tools.

Hope SystemVerilog standard be better :)

Best regards,
Davy

Jonathan Bromley wrote:
On 5 Dec 2006 03:07:08 -0800, "Davy" <zhushenli@gmail.com> wrote:

Hi all,

I use Clocking Block to construct testbench component like driver.
And I am confused with what time Clocking Block to synchronize data.

For example, there is "sync_fifo_if_i" interface instance and
"wr_driver_cb" clocking block.
The clocking block is
//-----
clocking wr_driver_cb @ (posedge clk);
default input #setup_time output #hold_time;
input full,almost_full;
output din,wr;
endclocking : wr_driver_cb
//-----


The data assignment sequence is
//-----

PLEASE, PLEASE tell me you are doing this from code running
in a program block. If the following code is running in a module,
then the SV LRM won't help you in deciding what happens. This
loophole will be fixed very soon, but right now it's not well defined.
ALWAYS use program code to access things through a clocking block.

@(sync_fifo_if_i.wr_driver_cb)

OK, this waits for the next posedge of clk as you expect.

din <= data_in;

NOOOOO! Don't do that! If you've created a clocking block,
then use it...

sync_fifo_if_i.wr_driver_cb.din <= data_in;

And then your "din" signal will correctly be driven #hold_time after
the clock edge.


The questions are
1. Will data assignment (synchronize) at the first @... or the second
@...theoretically?

If you do it correctly as I showed, the update to din will take place
#hold_time after the first @.

2. Is @(...) din<=data_in; and @(...); din<=data_in; (note the ;
difference in @) difference?

No, it's the same except that the semicolon gives you TWO
procedural statements (not one), so you might perhaps need
another begin...end. That's standard Verilog.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
 
On 19 Dec 2006 21:01:20 -0800, "Shenli" <zhushenli@gmail.com> wrote:

Hi Jonathan,

Thanks a lot for the suggestions!

I use sync_fifo_if_i.wr_driver_cb.din <= data_in; in my code. We know
that in program, clocking block assignment will schedule a
reactive-non-blocking-assignment just after #hold_time. And I guess in
module, clocking block assignment will do the same thing
Click to expand...
The SV-EC committee is actively working towards a reliable
definition that will do precisely that. Today, though, it's
ambiguous.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
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