SystemVerilog assignment to interface?

[Mark Curry]

All,

I've got a SystemVerilog question related to interfaces.

In my design I've got an array of interfaces:

interface foo_if();
// blah blah
modport master( /* blah */ );
modport slave( /* blah */ );
endinterface

foo_if foo_if_[ 3 : 0 ]();

I need to slice off ONE of the indices to go
to a subblock:

All's good:

foo_inst foo_inst ( .foo_if_( foo_if_[ 2 ] ) );

However, for reasons unsaid, I need to do this "assignment"
(for another index) again at this level to a new single interface:

foo_if foo_single_if_();

assign foo_single_if_ = foo_if_[ 1 ];

I can't find in the 2009 standard whether this is legal or not.
Two tools that I've used don't like it. I've tried
continous assignment ( which is what I see as happening "under the hood"
during an instancation), and a procedural assignment. Neither
works. Do I have to create a dummy module to just pick
instance array slices?

The tool needs to be smart in handling direction. But it does
that "magic" during the instanciation, and get's it right.
I'm thinking something with the modports, but I can't figure
it out. I DON'T want to resort to breaking the interface down
and assigning individual members - that ruins the whole point
of interfaces.

Thanks,

Mark

 

On Apr 23, 6:53 pm, gtw...@sonic.net (Mark Curry) wrote:

However, for reasons unsaid, I need to do this "assignment"
(for another index) again at this level to a new single interface:

foo_if foo_single_if_();

assign foo_single_if_ = foo_if_[ 1 ];

You can't do this, any more than you can assign one module instance to
another module instance. An interface instance is pretty much the
same thing as a module instance.

There is something called a virtual interface, which is a variable
that "points to" an interface. You can assign an interface to that,
which makes the virtual interface refer to that interface. And then
you can make references through the virtual interface pretty much as
if it were an interface. However, you cannot pass a virtual interface
through a module port. You can declare module ports to be of most
other variable types, but not a virtual interface type.

Which is actually rather strange, given that receiving an interface
passed through a port is very much like a virtual interface already.
It is just a "constant" virtual interface that is set at compile time
rather than run time. Like a virtual interface, it allows the lower
module to access the interface instance that was connected to it.

A virtual interface might give you what you are looking for. But it
probably isn't synthesizable.