SystemVerilog Assertions

[schop]

Veritools will be demonstrating powerful stand alone SystemVerilog
Assertion tools in Boston today and tomorrow. Demos will be held today,
September 19, at the Marriott in Newton, Mass. Designers of
SystemVerilog Assertions can also sign up for an onsite demo tomorrow,
although the number of still open slots available are limited. This
software was selected as one out of twelve of the most out standing new
software offerings at the recent DAC 43. As shown at DAC, this software
is estimated to be between 10 - 100 times faster when designers are
debugging their SystemVerilog Assertions over traditional simulator
only approaches. Send mail to request@veritools.com to find out how to
see a demo today or tomorrow on this stand alone SystemVerilog
Assertion software.

 

[Ajeetha]

Hi,

this software
is estimated to be between 10 - 100 times faster when designers are
debugging their SystemVerilog Assertions over traditional simulator
only approaches.

Interesting, would you be able to share any technical
whitepapers/screenshots to show us more? I'm based in Bangalore. FYI -
I've been using SVA/PSL for last 3+ years in consultancy/trainings with
4+ vendors.

Thanks
Ajeetha, CVC
www.noveldv.com
www.systemverilog.us