SystemVerilog Assertions and testbench

[Dudee Bastardo]

Hello All,

I am quite new in this area, and I need some help (just a simple one ).
I am doing my master thesis with a company, and I have to deal with
SystemVerilog Assertions. I have some quite good book about the topic, so more
or less I'm on my way to understand this verification method.
One thing is not clear enough for me (eheh..of course, not just only one), and I
ask your help:

Let's say I have a design in Verilog (for e.g a simple 4 bit counter) and a
testbench written in Verilog also that generates the testvectors in a separate
file.
Where can I put the SVA's? I think I can put it into the testbench file and into
the design also.
Is it possible to put it into a separate file?
In case yes, how to write the instantiation correctly? Can you show me some very
basic example?

Thx a lot!
G.

ps: Is there any tutorial dealing with these kind of things?

 

[Srinivasan Venkataramanan]

Hi,
Glad that you are doing Masters Thesis in a hot area like ABV/SVA. Quick
answer to your specific Q:

1. SV has "bind" construct to do what you asked for. I'm not sure which book
you refer to, our book does have examples on this use model (and much more
of-course).
2. Having said that, it is a good idea to have some assertions in RTL, some
in TB, some stand alone - again there are guidelines in our book.
3. If the company you are working with (doing your project with) is a SNPS
customer, you may want to take a regular SNPS course on SVA - that will
address lot of these Qs.
4. Check out www.project-veripage.com for a SVA tutorial.

HTH. Good Luck
Sri

--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned
"Dudee Bastardo" <gabor.dudas@fh-furtwangen.de> wrote in message
news:newscache$u1ntmi$xbh$1@news.ghb.fh-furtwangen.de...

Hello All,

I am quite new in this area, and I need some help (just a simple one ).
I am doing my master thesis with a company, and I have to deal with
SystemVerilog Assertions. I have some quite good book about the topic, so
more
or less I'm on my way to understand this verification method.
One thing is not clear enough for me (eheh..of course, not just only one),
and I
ask your help:

Let's say I have a design in Verilog (for e.g a simple 4 bit counter) and
a
testbench written in Verilog also that generates the testvectors in a
separate
file.
Where can I put the SVA's? I think I can put it into the testbench file
and into
the design also.
Is it possible to put it into a separate file?
In case yes, how to write the instantiation correctly? Can you show me
some very
basic example?

Thx a lot!
G.

ps: Is there any tutorial dealing with these kind of things?

 

[Dudee Bastardo]

Hello,

Now I know why your name was familiar
I just got the "SystemVerilog Assertion Handbook" 2 days ago..

Thanks for the help, and for the book also I will take a look into it. I am
using also the "Practical guide to SystemVerilog Assertions".

Both books are great.

Best Regards,
Dudee



Srinivasan Venkataramanan wrote:

Hi,
Glad that you are doing Masters Thesis in a hot area like ABV/SVA. Quick
answer to your specific Q:

1. SV has "bind" construct to do what you asked for. I'm not sure which book
you refer to, our book does have examples on this use model (and much more
of-course).
2. Having said that, it is a good idea to have some assertions in RTL, some
in TB, some stand alone - again there are guidelines in our book.
3. If the company you are working with (doing your project with) is a SNPS
customer, you may want to take a regular SNPS course on SVA - that will
address lot of these Qs.
4. Check out www.project-veripage.com for a SVA tutorial.

HTH. Good Luck
Sri