Systemverilog assertion property and interface/modport?

T

talkb

Guest
Can Systemverilog properties (assertions) accept interface/modport
arguments?

property prop_sum1( clk, resetn, x, y, z );
disable iff ( resetn ) @( posedge clk ) x + y === z;
endproperty : my_prop

aprop_sum1 : assert property( prop_sum1( ... ) ) else
$error ( "%m: property failed!" );

For example, is there a way to replace "clk, resetn, x, y, z" with an
interface/modport?
Is that a standardized (IEEE 1800-2005) feature, or is it something that is
a vendor-
specific extension?
 
On Fri, 01 Feb 2008 05:13:11 GMT, "talkb" <noone@talkb.com> wrote:

Can Systemverilog properties (assertions) accept interface/modport
arguments?

property prop_sum1( clk, resetn, x, y, z );
disable iff ( resetn ) @( posedge clk ) x + y === z;
endproperty : my_prop

aprop_sum1 : assert property( prop_sum1( ... ) ) else
$error ( "%m: property failed!" );

For example, is there a way to replace "clk, resetn, x, y, z" with an
interface/modport?
Click to expand...
I don't believe so.

Arguments to properties work in a very similar way to
text macro substitution, so you might care to try this -
but I don't think it is supported by the language standard:

property prop_sum1( MP );
disable iff ( MP.resetn ) @( posedge MP.clk ) MP.x + MP.y === MP.z;
endproperty : my_prop

and then supply an interface.modport instance when you
instantiate the property.

A better alternative would be to hide the property inside
a module (or interface), have the property reference
components of a modport port on the module, and then
instantiate the module connecting it to the required
interface.modport instance.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Feb 11, 12:16 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
On Fri, 01 Feb 2008 05:13:11 GMT, "talkb" <no...@talkb.com> wrote:
Can Systemverilog properties (assertions) accept interface/modport
arguments?

property prop_sum1( clk, resetn, x, y, z );
 disable iff ( resetn ) @( posedge clk ) x + y === z;
endproperty : my_prop

aprop_sum1 : assert property( prop_sum1( ... ) ) else
  $error ( "%m: property failed!" );

For example, is there a way to replace "clk, resetn, x, y, z" with an
interface/modport?

I don't believe so.

Arguments to properties work in a very similar way to
text macro substitution, so you might care to try this -
but I don't think it is supported by the language standard:

 property prop_sum1( MP );
   disable iff ( MP.resetn ) @( posedge MP.clk ) MP.x + MP.y === MP.z;
 endproperty : my_prop

and then supply an interface.modport instance when you
instantiate the property.

A better alternative would be to hide the property inside
a module (or interface), have the property reference
components of a modport port on the module, and then
instantiate the module connecting it to the required
interface.modport instance.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
Hi,
I have a similar problem.
I am trying to make the clock accessed through an interface as the
clocking event for my assertion(property)
But it looks like this is not allowed.
My code is something like this..

property p1;
@(posedge interface.clk) S1|=>S2;
endproperty

I get an error saying that the property cannot have real, dynamic SV
types and events as clocking events..
The above property is inside a PROGRAM block..
Is it not possible to access a clock which is visible in a program
from teh assertion?

Rakesh
 
On Mon, 11 Feb 2008 00:22:09 -0800 (PST),
rakesh <rakeshmg@gmail.com> wrote:

I am trying to make the clock accessed through an interface as the
clocking event for my assertion(property)
But it looks like this is not allowed.
My code is something like this..

property p1;
@(posedge interface.clk) S1|=>S2;
Click to expand...
Not literally "interface.clk", I hope - you're using the
name of an interface INSTANCE, surely?

endproperty

I get an error saying that the property cannot have real, dynamic SV
types and events as clocking events..
The above property is inside a PROGRAM block..
Is it not possible to access a clock which is visible in a program
from teh assertion?
Click to expand...
I would need to check on the exact details, but in any case there's
a better way to do it.

Create a clocking block in the interface, and put the property
in that interface:

interface test_access_intf(input bit clk);
logic S1, S2;
default clocking TA_cb @(posedge clk);
input S1, S2; // with default #1step sampling,
// mandatory for assertions
endclocking
property p1; @(TA_cb) S1 |=> S2; endproperty
endinterface

Now you can see the property from a connected program:

program P;
....
A1: assert property (intf.p1);

This usually makes pretty good sense, because properties are
often attached to a bunch of signals that are in an interface
because you expect to re-use the interface elsewhere.

hth
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Feb 11, 2:14 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
On Mon, 11 Feb 2008 00:22:09 -0800 (PST),

rakesh <rakes...@gmail.com> wrote:
I am trying to make the clock accessed through an interface as the
clocking event for my assertion(property)
But it looks like this is not allowed.
My code is something like this..

property p1;
@(posedge interface.clk) S1|=>S2;

Not literally "interface.clk", I hope - you're using the
name of an interface INSTANCE, surely?

endproperty

I get an error saying that the property cannot have real, dynamic SV
types and events as clocking events..
The above property is inside a PROGRAM block..
Is it not possible to access a clock which is visible in a program
from teh assertion?

I would need to check on the exact details, but in any case there's
a better way to do it.

Create a clocking block in the interface, and put the property
in that interface:

  interface test_access_intf(input bit clk);
    logic S1, S2;
    default clocking TA_cb @(posedge clk);
      input S1, S2;  // with default #1step sampling,
                     // mandatory for assertions
    endclocking
    property p1; @(TA_cb) S1 |=> S2; endproperty
  endinterface

Now you can see the property from a connected program:

  program P;
    ....
    A1: assert property (intf.p1);

This usually makes pretty good sense, because properties are
often attached to a bunch of signals that are in an interface
because you expect to re-use the interface elsewhere.

hth
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.  
Click to expand...
Hi Jonathan,
Thanks for the reply.

I am using an instance of the interface.. ;-)

I don't want to add these assertions to the interface as they are very
test specific. I don't want to run them when i am tesing someother
block connected to the interface, i know you would suggest disabling
the assertions, but i want to have the assertions completely in the
test(program block).

I thought it was correct to use the clock(or any other signal from the
interface) as a clocking item for the assertions, but i think this is
not teh case..
anyway if you can tell me whether it is allowed, it would help me a
lot.

Rakesh
 
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