SystemVerilog arrays

Guest
Perhaps somebody could explain the following?

My SystemVerilog simulator complains about line 13 but not line 12?
It indicates that line 13's access to 'd' has the "wrong number of
indices"? Am I missing something obvious here?
(A corner case I agree but one that I need in a parameterized design)

- Robert.

module test();

parameter N=1;

logic [7:0] a;
logic [1:0][1:0] b;
logic [1:0][N-1:0][1:0] c; // fine
logic [1:0][N-1:0][N-1:0][1:0] d; // complains?

assign a[0]=b[1][1];
assign a[1]=c[1][0][1]; // line 12
assign a[2]=d[1][0][0][1]; // line 13

endmodule
 
On 8 May 2007 08:55:54 -0700, Robert.Mullins@gmail.com wrote:

Perhaps somebody could explain the following?

My SystemVerilog simulator complains about line 13 but not line 12?
It indicates that line 13's access to 'd' has the "wrong number of
indices"? Am I missing something obvious here?
(A corner case I agree but one that I need in a parameterized design)

- Robert.

module test();

parameter N=1;

logic [7:0] a;
logic [1:0][1:0] b;
logic [1:0][N-1:0][1:0] c; // fine
logic [1:0][N-1:0][N-1:0][1:0] d; // complains?

assign a[0]=b[1][1];
assign a[1]=c[1][0][1]; // line 12
assign a[2]=d[1][0][0][1]; // line 13
Click to expand...
I agree that your code looks OK. It seems as though
the simulator is setting an arbitrary limit of 3 on the
number of packed dimensions, or something.

However, I do somewhat wonder what you're doing with 4
packed dimensions...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message
news:b3b1439lbc4mnkcni8g0iuahp3ng5ugkjh@4ax.com...
On 8 May 2007 08:55:54 -0700, Robert.Mullins@gmail.com wrote:

My SystemVerilog simulator complains about line 13 but not line 12?
It indicates that line 13's access to 'd' has the "wrong number of
indices"? Am I missing something obvious here?
(A corner case I agree but one that I need in a parameterized design)

parameter N=1;

logic [7:0] a;
logic [1:0][1:0] b;
logic [1:0][N-1:0][1:0] c; // fine
logic [1:0][N-1:0][N-1:0][1:0] d; // complains?

assign a[0]=b[1][1];
assign a[1]=c[1][0][1]; // line 12
assign a[2]=d[1][0][0][1]; // line 13

I agree that your code looks OK. It seems as though
the simulator is setting an arbitrary limit of 3 on the
number of packed dimensions, or something.
Click to expand...
Which simulator are you using?

Altera Quartus-II 7.1 (Web) edition doesn't support Systemverilog
packed-arrays at all.
It still supports packed 2D-arrays (for synthesis) from Verilog-2001.
 
On 13 May, 21:28, "Xilinx user" <xilinx_u...@nowhere.net> wrote:
"Jonathan Bromley" <jonathan.brom...@MYCOMPANY.com> wrote in message

news:b3b1439lbc4mnkcni8g0iuahp3ng5ugkjh@4ax.com...



On 8 May 2007 08:55:54 -0700, Robert.Mull...@gmail.com wrote:

My SystemVerilog simulator complains about line 13 but not line 12?
It indicates that line 13's access to 'd' has the "wrong number of
indices"? Am I missing something obvious here?
(A corner case I agree but one that I need in a parameterized design)

parameter N=1;

logic [7:0] a;
logic [1:0][1:0] b;
logic [1:0][N-1:0][1:0] c; // fine
logic [1:0][N-1:0][N-1:0][1:0] d; // complains?

assign a[0]=b[1][1];
assign a[1]=c[1][0][1]; // line 12
assign a[2]=d[1][0][0][1]; // line 13

I agree that your code looks OK. It seems as though
the simulator is setting an arbitrary limit of 3 on the
number of packed dimensions, or something.

Which simulator are you using?
Altera Quartus-II 7.1 (Web) edition doesn't support Systemverilog
packed-arrays at all.
It still supports packed 2D-arrays (for synthesis) from Verilog-2001
Click to expand...
I also have an interest in targeting FPGAs. Anyone have any experience
of using SystemVerilog on FPGAs? What is the best route to take here?

(1) Initial synthesis in DC -> DC-FPGA -> Quartus/Xilinx tools
(2) Mentor's Precision RTL
(3) Synplicity's Synthesis tool?

- Robert
 
On 13 May, 21:28, "Xilinx user" <xilinx_u...@nowhere.net> wrote:
"Jonathan Bromley" <jonathan.brom...@MYCOMPANY.com> wrote in message

news:b3b1439lbc4mnkcni8g0iuahp3ng5ugkjh@4ax.com...



On 8 May 2007 08:55:54 -0700, Robert.Mull...@gmail.com wrote:

My SystemVerilog simulator complains about line 13 but not line 12?
It indicates that line 13's access to 'd' has the "wrong number of
indices"? Am I missing something obvious here?
(A corner case I agree but one that I need in a parameterized design)

parameter N=1;

logic [7:0] a;
logic [1:0][1:0] b;
logic [1:0][N-1:0][1:0] c; // fine
logic [1:0][N-1:0][N-1:0][1:0] d; // complains?

assign a[0]=b[1][1];
assign a[1]=c[1][0][1]; // line 12
assign a[2]=d[1][0][0][1]; // line 13

I agree that your code looks OK. It seems as though
the simulator is setting an arbitrary limit of 3 on the
number of packed dimensions, or something.

Which simulator are you using?
Altera Quartus-II 7.1 (Web) edition doesn't support Systemverilog
packed-arrays at all.
It still supports packed 2D-arrays (for synthesis) from Verilog-2001
Click to expand...
I also have an interest in targeting FPGAs. Anyone have any experience
of using SystemVerilog on FPGAs? What is the best route to take here?

(1) Initial synthesis in DC -> DC-FPGA -> Quartus/Xilinx tools
(2) Mentor's Precision RTL
(3) Synplicity's Synthesis tool?

- Robert
 
On May 14, 2:23 am, Robert.Mull...@gmail.com wrote:
On 13 May, 21:28, "Xilinx user" <xilinx_u...@nowhere.net> wrote:



"Jonathan Bromley" <jonathan.brom...@MYCOMPANY.com> wrote in message

news:b3b1439lbc4mnkcni8g0iuahp3ng5ugkjh@4ax.com...

On 8 May 2007 08:55:54 -0700, Robert.Mull...@gmail.com wrote:

My SystemVerilog simulator complains about line 13 but not line 12?
It indicates that line 13's access to 'd' has the "wrong number of
indices"? Am I missing something obvious here?
(A corner case I agree but one that I need in a parameterized design)

parameter N=1;

logic [7:0] a;
logic [1:0][1:0] b;
logic [1:0][N-1:0][1:0] c; // fine
logic [1:0][N-1:0][N-1:0][1:0] d; // complains?

assign a[0]=b[1][1];
assign a[1]=c[1][0][1]; // line 12
assign a[2]=d[1][0][0][1]; // line 13

I agree that your code looks OK. It seems as though
the simulator is setting an arbitrary limit of 3 on the
number of packed dimensions, or something.

Which simulator are you using?
Altera Quartus-II 7.1 (Web) edition doesn't support Systemverilog
packed-arrays at all.
It still supports packed 2D-arrays (for synthesis) from Verilog-2001

I also have an interest in targeting FPGAs. Anyone have any experience
of using SystemVerilog on FPGAs? What is the best route to take here?

(1) Initial synthesis in DC -> DC-FPGA -> Quartus/Xilinx tools
(2) Mentor's Precision RTL
(3) Synplicity's Synthesis tool?
Click to expand...
Robert,

I've used Mentor Precision for a SystemVerilog FPGA design with great
success.
We evaluated both your other options. DC_FPGA is basically EOL, and
no longer offered.
Synplicity seems to have no desire at all to support SystemVerilog at
this point in time.

XST 10 is supposed to start adding SystemVerilog too.

--Mark
 
On 14 May 2007 09:48:16 -0700,
<gtwrek@pacbell.net> wrote:


I've used Mentor Precision for a SystemVerilog FPGA design with great
success.
We evaluated both your other options. DC_FPGA is basically EOL, and
no longer offered.
Click to expand...
In fairness, DC's support for SystemVerilog synthesis has been
seriously useful for quite a while now. I know that's no
comfort to people targeting FPGAs, though, since (as you say)
DC-FPGA is moribund.

Synplicity seems to have no desire at all to support SystemVerilog at
this point in time.
Click to expand...
They have some limited feature support. It's clear that they
don't see much pull from their user base. I really, really
don't understand why this is so; the synthesis features of
SystemVerilog are the obvious low-hanging fruit for many
users. Right now I'm not using *any* synthesis tool in anger
on any real project, but if I were (and I surely will be,
some time soon) I know I would be beating on Synplicity's door
asking why they can't do a lot more of the easy stuff
than they currently do. Am I isolated in perceiving the
Verilog designer user base as being remarkably conservative
and set in their ways? (Note *designer* - the verification
folk are, typically, extremely enthusiastic adopters of
powerful new techniques if they show enough promise.)

XST 10 is supposed to start adding SystemVerilog too.
Click to expand...
I would *love* to know the distribution of the XST and
Quartus user base over Verilog vs. VHDL. Many (but, of
course, not all) of the things that SystemVerilog offers
to designers have been a part of VHDL for years, and it
may be simply that FPGA users are so overwhelmingly
VHDL-oriented that there's no strong pull on the vendors
to implement SV. Maybe that's why Synplicity are not
putting obvious emphasis on it?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Jonathan Bromley wrote:

I would *love* to know the distribution of the XST and
Quartus user base over Verilog vs. VHDL. Many (but, of
course, not all) of the things that SystemVerilog offers
to designers have been a part of VHDL for years, and it
may be simply that FPGA users are so overwhelmingly
VHDL-oriented that there's no strong pull on the vendors
to implement SV. Maybe that's why Synplicity are not
putting obvious emphasis on it?
Click to expand...
Based on a very small sample size, I would guess
that VHDL has a slight majority for FPGA designers.
However it is rare to see a design that makes
any use of VHDL's advantages, so I guess I'm
not surprised about the weak demand for SV.

There is still a gap between designers
with hardware skills and those with computer
science skills. Many fpga designers still
validate their designs on the bench using
hardware logic analysis of one type or another.

-- Mike Treseler
 
On May 14, 5:23 am, Robert.Mull...@gmail.com wrote:
(1) Initial synthesis in DC -> DC-FPGA -> Quartus/Xilinx tools
(2) Mentor's Precision RTL
(3) Synplicity's Synthesis tool?
Click to expand...
(4) Quartus II Integrated Synthesis

I evaluated Quartus' SV support in 6.1. I submitted a few bug reports
and they assured me that they would be fixed in 7.1. I guess I'll give
it another go eventually. You'll find the supported language features
somewhere hidden in the documentation, they list the sections of the
IEEE-SV standard that they implement.

I've also used (2) and despite its horrible name mangling (try using
parameterized interfaces), cryptic error messages and the fact that it
sometimes segfaults when your code is incorrect, as a whole, it seems
to do the trick. However, I am having some problems instantiating a
black box PLL from the altera_mf library. Precision's support for
Xilinx DCM's seems to be better implemented.

Edmond
 
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