Systemverilog `__LINE__ and `__FILE__ preprocessor tokens

[fpg]

I just discovered the convenience of `__LINE__ and `__FILE__, something
ANSI-C progarmmers have known about for a long time.

`define DEBUG_STAMP `__FILE__,":",`__LINE__
module x;
const int y = 32;

begin : main_block

$display( `DEBUG_STAMP," error encountered here!" );
$display( `DEBUG_STAMP," second error encountered here!" );

end : main_block
endmodule : x
....

/lsi/snspc/proj/mytest.sv:41 error encountered here!
/lsi/snspc/proj/mytest.sv:42 second error encountered here!

Sadly, my simple module didn't compile in Cadence IUS 6.20-s003 --
perhaps I did not issue the proper command-line switches...
If I remove the offending `DEBUG_STAMP definition and references to,
it simulates ok. (I ran a test file with both "ncverilog +sv"and the
newer preferred "irun myfile.sv")

Amusing that the FPGA-class simulators (Modelsim/PE, Aldec Active-HDL 7.3)
handled it just fine. (Of course, neither of these simulators support
the class/endclass testbench-constructs all that well, or at all.)

 

On Feb 9, 12:33 am, "fpg" <f...@pcb.net> wrote:

I just discovered the convenience of `__LINE__ and `__FILE__, something
ANSI-C progarmmers have known about for a long time.

Amusing that the FPGA-class simulators (Modelsim/PE, Aldec Active-HDL 7.3)
handled it just fine.  (Of course, neither of these simulators support
the class/endclass testbench-constructs all that well, or at all.)

These are not part of the SystemVerilog standard yet.

 

[Dwayne Dilbeck]

I just did a search in the IEEE1800, IEEE1364-2005, and SystemVerilog 3.1a
PDF documents. Based on that I would say they are not actually defined. Yet
a google search gives results in a "vppp" program that claims they were
defined in 1364-2005 and Systemverilog 3.1a.

Could somone post the section that describes these functions? I am not
finding it.

All of which returned a negative result for "__FILE__" or "__LINE__".
"fpg" <fpg@pcb.net> wrote in message
news:2Xarj.55097$Pv2.18758@newssvr23.news.prodigy.net...

I just discovered the convenience of `__LINE__ and `__FILE__, something
ANSI-C progarmmers have known about for a long time.

`define DEBUG_STAMP `__FILE__,":",`__LINE__
module x;
const int y = 32;

begin : main_block

$display( `DEBUG_STAMP," error encountered here!" );
$display( `DEBUG_STAMP," second error encountered here!" );

end : main_block
endmodule : x
...

/lsi/snspc/proj/mytest.sv:41 error encountered here!
/lsi/snspc/proj/mytest.sv:42 second error encountered here!

Sadly, my simple module didn't compile in Cadence IUS 6.20-s003 --
perhaps I did not issue the proper command-line switches...
If I remove the offending `DEBUG_STAMP definition and references to,
it simulates ok. (I ran a test file with both "ncverilog +sv"and the
newer preferred "irun myfile.sv")

Amusing that the FPGA-class simulators (Modelsim/PE, Aldec Active-HDL 7.3)
handled it just fine. (Of course, neither of these simulators support
the class/endclass testbench-constructs all that well, or at all.)

 

[Dwayne Dilbeck]

Ah...the "vppp" website explains that these are not defined by System
verilog, the `__FILE__ and `__LINE__ constructs are extensions to the
language. Thus why IUS doesn't regonize them.

"Dwayne Dilbeck" <ddilbeck@yahoo.com> wrote in message
news:13r41b8clp449e9@corp.supernews.com...

I just did a search in the IEEE1800, IEEE1364-2005, and SystemVerilog 3.1a
PDF documents. Based on that I would say they are not actually defined.
Yet a google search gives results in a "vppp" program that claims they were
defined in 1364-2005 and Systemverilog 3.1a.

Could somone post the section that describes these functions? I am not
finding it.

All of which returned a negative result for "__FILE__" or "__LINE__".
"fpg" <fpg@pcb.net> wrote in message
news:2Xarj.55097$Pv2.18758@newssvr23.news.prodigy.net...
I just discovered the convenience of `__LINE__ and `__FILE__, something
ANSI-C progarmmers have known about for a long time.

`define DEBUG_STAMP `__FILE__,":",`__LINE__
module x;
const int y = 32;

begin : main_block

$display( `DEBUG_STAMP," error encountered here!" );
$display( `DEBUG_STAMP," second error encountered here!" );

end : main_block
endmodule : x
...

/lsi/snspc/proj/mytest.sv:41 error encountered here!
/lsi/snspc/proj/mytest.sv:42 second error encountered here!

Sadly, my simple module didn't compile in Cadence IUS 6.20-s003 --
perhaps I did not issue the proper command-line switches...
If I remove the offending `DEBUG_STAMP definition and references to,
it simulates ok. (I ran a test file with both "ncverilog +sv"and the
newer preferred "irun myfile.sv")

Amusing that the FPGA-class simulators (Modelsim/PE, Aldec Active-HDL
7.3)
handled it just fine. (Of course, neither of these simulators support
the class/endclass testbench-constructs all that well, or at all.)

 

On Feb 12, 3:58 pm, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote:

Ah...the "vppp"  website explains that these are not defined by System
verilog, the `__FILE__ and `__LINE__ constructs are extensions to the
language.  Thus why IUS doesn't regonize them.

A proposal to add them to the draft for the next standard was approved
at the committee level in November.