systemc , verilog or systemverilog

i've started using verilog around 6 months back and used it to design
simple to moderately complex digital systems. As the design gets more
complex, i faced lot of problems in verifying the it with verilog as
the things i could do for verification is limited(at least to my
knowledge. It may be that im lacking the required knowledge on
techniques used for verification. please let me know if any one know
any resources where i can get that knowledge). For this reason i
wanted to move on to systemverilog, and started learning it. i was
surprised by the new feature set and started looking for good
simulators for it and found none that i could use (as im almost a
student). therefore im now considering the use of systemc for this
purpose. however im confused about the use of systemC. i need to know
1) the design/implementation flow with systemC.
2) with systemverilog, we are interacting with the actual RTL code
that will be synthesized and implemented, so any test that is
performed is valid for the actual implementation as well. but with
systemC, it seems like we are emulating the actual system we want and
perform tests on it and do a functional verification. when this is
done, we need to convert that systemC description to RTL code that
could be synthesized. i need to know about the typical effort required
in this transformation step, assuming im not going to depend on
synthesizable subset of systemC.
3) Is errors that can be found by systemC a subset of errors found
using systemverilog? can systemC support non-functional verification
like timing verification. If so is it a standard way of doing it?

hope someone can help me with these questions.
thank you.

 

[mjl296@hotmail.com]

On 11 Oct, 21:30, e2po...@yahoo.com wrote:

i've started using verilog around 6 months back and used it to design
simple to moderately complex digital systems. As the design gets more
complex, i faced lot of problems in verifying the it with verilog as
the things i could do for verification is limited(at least to my
knowledge. It may be that im lacking the required knowledge on
techniques used for verification. please let me know if any one know
any resources where i can get that knowledge). For this reason i
wanted to move on to systemverilog, and started learning it. i was
surprised by the new feature set and started looking for good
simulators for it and found none that i could use (as im almost a
student). therefore im now considering the use of systemc for this
purpose. however im confused about the use of systemC. i need to know
1) the design/implementation flow with systemC.
2) with systemverilog, we are interacting with the actual RTL code
that will be synthesized and implemented, so any test that is
performed is valid for the actual implementation as well. but with
systemC, it seems like we are emulating the actual system we want and
perform tests on it and do a functional verification. when this is
done, we need to convert that systemC description to RTL code that
could be synthesized. i need to know about the typical effort required
in this transformation step, assuming im not going to depend on
synthesizable subset of systemC.
3) Is errors that can be found by systemC a subset of errors found
using systemverilog? can systemC support non-functional verification
like timing verification. If so is it a standard way of doing it?

hope someone can help me with these questions.
thank you.

The excitement about SystemVerilog and SystemC is justified. Both
languages give you powerful features for behavioural modelling, and
SystemVerilog adds lots of powerful random test generation constructs
and functional coverage constructs.

That said, you must not forget that plenty of big chips are still
verified using vanilla Verilog and VHDL. Many companies are still only
beginning to look at SystemVerilog and SystemC, and have been
producing successful products without these tools for years. If you
are stuck with free tools, you may find that this is your best
approach. You could consider using C/C++ or another software language
to create test vectors that you then play through the DUT using
Verilog.

In my experience, both SystemVerilog and SystemC are used to model the
behaviour of a system in the early stages of the design process. As
the design matures, components of the system are refined into RTL for
synthesis, but the test fixtures that were used for the behavioural
models remain. In both cases, the SystemC/SystemVerilog is simulated
alongside the sythesisable RTL in the same simulation. With
SystemVerilog this is easy to understand - Verilog is a subset of the
language. With SystemC, you require access to a simulator that
understands both languages.

On a budget, you may find it difficult to find a simulator that
supports SystemVerilog, or mixed simulation of SystemC with Verilog -
other members of the group may be able to suggest free/cheap tools
that support this. I personally have used ModelSim, Questa and VCS for
this task, but none are cheap.

In theory it is possible to write SystemC at the RTL level, and you
could simulate this with any C++ compiler. However, you won't find a
synthesis tool that accepts it, so it is of little use.

On balance, I suspect that if you don't have the budget for the big
guns, then you are probably best using some mix of C modelling and
vanilla Verilog to test your device.

I hope this is of some help.

Mark

The excitement about SystemVerilog and SystemC is justified. Both
languages give you powerful features for behavioural modelling, and
SystemVerilog adds lots of powerful random test generation constructs
and functional coverage constructs.

That said, you must not forget that plenty of big chips are still
verified using vanilla Verilog and VHDL. Many companies are still only
beginning to look at SystemVerilog and SystemC, and have been
producing successful products without these tools for years. If you
are stuck with free tools, you may find that this is your best
approach. You could consider using C/C++ or another software language
to create test vectors that you then play through the DUT using
Verilog.

In my experience, both SystemVerilog and SystemC are used to model the
behaviour of a system in the early stages of the design process. As
the design matures, components of the system are refined into RTL for
synthesis, but the test fixtures that were used for the behavioural
models remain. In both cases, the SystemC/SystemVerilog is simulated
alongside the sythesisable RTL in the same simulation. With
SystemVerilog this is easy to understand - Verilog is a subset of the
language. With SystemC, you require access to a simulator that
understands both languages.

On a budget, you may find it difficult to find a simulator that
supports SystemVerilog, or mixed simulation of SystemC with Verilog -
other members of the group may be able to suggest free/cheap tools
that support this. I personally have used ModelSim, Questa and VCS for
this task, but none are cheap.

In theory it is possible to write SystemC at the RTL level, and you
could simulate this with any C++ compiler. However, you won't find a
synthesis tool that accepts it, so it is of little use.

On balance, I suspect that if you don't have the budget for the big
guns, then you are probably best using some mix of C modelling and
vanilla Verilog to test your device.

I hope this is of some help.

Mark

 

[mjl296@hotmail.com]

On 12 Oct, 13:36, "mjl...@hotmail.com" <mjl...@hotmail.com> wrote:

On 11 Oct, 21:30, e2po...@yahoo.com wrote:



i've started using verilog around 6 months back and used it to design
simple to moderately complex digital systems. As the design gets more
complex, i faced lot of problems in verifying the it with verilog as
the things i could do for verification is limited(at least to my
knowledge. It may be that im lacking the required knowledge on
techniques used for verification. please let me know if any one know
any resources where i can get that knowledge). For this reason i
wanted to move on to systemverilog, and started learning it. i was
surprised by the new feature set and started looking for good
simulators for it and found none that i could use (as im almost a
student). therefore im now considering the use of systemc for this
purpose. however im confused about the use of systemC. i need to know
1) the design/implementation flow with systemC.
2) with systemverilog, we are interacting with the actual RTL code
that will be synthesized and implemented, so any test that is
performed is valid for the actual implementation as well. but with
systemC, it seems like we are emulating the actual system we want and
perform tests on it and do a functional verification. when this is
done, we need to convert that systemC description to RTL code that
could be synthesized. i need to know about the typical effort required
in this transformation step, assuming im not going to depend on
synthesizable subset of systemC.
3) Is errors that can be found by systemC a subset of errors found
using systemverilog? can systemC support non-functional verification
like timing verification. If so is it a standard way of doing it?

hope someone can help me with these questions.
thank you.

The excitement about SystemVerilog and SystemC is justified. Both
languages give you powerful features for behavioural modelling, and
SystemVerilog adds lots of powerful random test generation constructs
and functional coverage constructs.

That said, you must not forget that plenty of big chips are still
verified using vanilla Verilog and VHDL. Many companies are still only
beginning to look at SystemVerilog and SystemC, and have been
producing successful products without these tools for years. If you
are stuck with free tools, you may find that this is your best
approach. You could consider using C/C++ or another software language
to create test vectors that you then play through the DUT using
Verilog.

In my experience, both SystemVerilog and SystemC are used to model the
behaviour of a system in the early stages of the design process. As
the design matures, components of the system are refined into RTL for
synthesis, but the test fixtures that were used for the behavioural
models remain. In both cases, the SystemC/SystemVerilog is simulated
alongside the sythesisable RTL in the same simulation. With
SystemVerilog this is easy to understand - Verilog is a subset of the
language. With SystemC, you require access to a simulator that
understands both languages.

On a budget, you may find it difficult to find a simulator that
supports SystemVerilog, or mixed simulation of SystemC with Verilog -
other members of the group may be able to suggest free/cheap tools
that support this. I personally have used ModelSim, Questa and VCS for
this task, but none are cheap.

In theory it is possible to write SystemC at the RTL level, and you
could simulate this with any C++ compiler. However, you won't find a
synthesis tool that accepts it, so it is of little use.

On balance, I suspect that if you don't have the budget for the big
guns, then you are probably best using some mix of C modelling and
vanilla Verilog to test your device.

I hope this is of some help.

Mark

The excitement about SystemVerilog and SystemC is justified. Both
languages give you powerful features for behavioural modelling, and
SystemVerilog adds lots of powerful random test generation constructs
and functional coverage constructs.

That said, you must not forget that plenty of big chips are still
verified using vanilla Verilog and VHDL. Many companies are still only
beginning to look at SystemVerilog and SystemC, and have been
producing successful products without these tools for years. If you
are stuck with free tools, you may find that this is your best
approach. You could consider using C/C++ or another software language
to create test vectors that you then play through the DUT using
Verilog.

In my experience, both SystemVerilog and SystemC are used to model the
behaviour of a system in the early stages of the design process. As
the design matures, components of the system are refined into RTL for
synthesis, but the test fixtures that were used for the behavioural
models remain. In both cases, the SystemC/SystemVerilog is simulated
alongside the sythesisable RTL in the same simulation. With
SystemVerilog this is easy to understand - Verilog is a subset of the
language. With SystemC, you require access to a simulator that
understands both languages.

On a budget, you may find it difficult to find a simulator that
supports SystemVerilog, or mixed simulation of SystemC with Verilog -
other members of the group may be able to suggest free/cheap tools
that support this. I personally have used ModelSim, Questa and VCS for
this task, but none are cheap.

In theory it is possible to write SystemC at the RTL level, and you
could simulate this with any C++ compiler. However, you won't find a
synthesis tool that accepts it, so it is of little use.

On balance, I suspect that if you don't have the budget for the big
guns, then you are probably best using some mix of C modelling and
vanilla Verilog to test your device.

I hope this is of some help.

Mark

Just to clarify, when I talked about refining SystemC/SystemVerilog
behavioural models into RTL - I meant Verilog or VHDL RTL.

Also, sorry about the double posting

 

[Mike Treseler]

e2point@yahoo.com wrote:

i've started using verilog around 6 months back and used it to design
simple to moderately complex digital systems. As the design gets more
complex, i faced lot of problems in verifying the it with verilog as
the things i could do for verification is limited(at least to my
knowledge. It may be that im lacking the required knowledge on
techniques used for verification. please let me know if any one know
any resources where i can get that knowledge).

I use plain vhdl for simulation.
example:
http://home.comcast.net/~mike_treseler/test_uart.vhd

I prefer a single verification process (block)
using local variables and lots of procedures(tasks).
I have not had a reason to try this style in verilog
but I see no obvious reason why it would not work.

i wanted to move on to systemverilog, and started learning it. i was
surprised by the new feature set and started looking for good
simulators for it and found none that i could use (as im almost a
student). therefore im now considering the use of systemc for this
purpose.

There are some advantages to systemverilog and systemc,
but simplicity of process and low cost are not yet included.

-- Mike Treseler

 

[HT-Lab]

Some minor additions,

<mjl296@hotmail.com> wrote in message
news:1192192606.728998.203260@q5g2000prf.googlegroups.com...

On 11 Oct, 21:30, e2po...@yahoo.com wrote:
i've started using verilog around 6 months back and used it to design
...snip

On a budget, you may find it difficult to find a simulator that
supports SystemVerilog, or mixed simulation of SystemC with Verilog -
other members of the group may be able to suggest free/cheap tools
that support this. I personally have used ModelSim, Questa and VCS for
this task, but none are cheap.

In theory it is possible to write SystemC at the RTL level, and you
could simulate this with any C++ compiler. However, you won't find a
synthesis tool that accepts it, so it is of little use.

There are a number of SystemC synthesis tools available ranging from the
low'ish cost SystemCrafters up to $$$ ForteDS. There is also a SystemC
Synthesis standard draft.

Hans
www.ht-lab.com

On balance, I suspect that if you don't have the budget for the big
guns, then you are probably best using some mix of C modelling and
vanilla Verilog to test your device.

I hope this is of some help.

Mark

 

That said, you must not forget that plenty of big chips are still
verified using vanilla Verilog and VHDL. Many companies are still only
beginning to look at SystemVerilog and SystemC, and have been
producing successful products without these tools for years.
are stuck with free tools, you may find that this is your best
approach.

do the companies seriously consider system verilog approaches?

You could consider using C/C++ or another software language
to create test vectors that you then play through the DUT using
Verilog.

how do we do that? do i need to have a compiler which support both c++
and verilog
OR we use facilities provided by verilog for c interfacing?


any way, this is the exact information i was looking for.
thank you very much for the long descriptive explanation.

 

The excitement about SystemVerilog and SystemC is justified. Both
languages give you powerful features for behavioural modelling, and
SystemVerilog adds lots of powerful random test generation constructs
and functional coverage constructs.

one last question
what is i start learning vhdl instead? how does vhdl compare with
systemverilog?

 

[Robert Miles]

<e2point@yahoo.com> wrote in message
news:1192274801.669362.39770@q3g2000prf.googlegroups.com...

The excitement about SystemVerilog and SystemC is justified. Both
languages give you powerful features for behavioural modelling, and
SystemVerilog adds lots of powerful random test generation constructs
and functional coverage constructs.

one last question
what is i start learning vhdl instead? how does vhdl compare with
systemverilog?

There's a newsgroup comp.lang.vhdl that may help.

 

[Mike Treseler]

e2point@yahoo.com wrote:

The excitement about SystemVerilog and SystemC is justified. Both
languages give you powerful features for behavioural modelling, and
SystemVerilog adds lots of powerful random test generation constructs
and functional coverage constructs.

one last question
what is i start learning vhdl instead? how does vhdl compare with
systemverilog?

Learning vhdl instead, would cover most of the same
ground for less time and money. It would also allow you to
use low cost tools that are well understood and
already have most of the kinks worked out.
Here's some examples to get you started:
http://home.comcast.net/~mike_treseler/

Systemverilog does have some built-in simulation features that
I had to write code to cover in vhdl.
However it is but mostly a game of catch-up.
Most of the "new" sv language features have
been covered by tools for ten years.

-- Mike Treseler

 

[Mike Treseler]

Mike Treseler wrote:

been covered by tools for ten years.
^

vhdl

 

[mjl296@hotmail.com]

On 13 Oct, 16:55, Mike Treseler <mike_trese...@comcast.net> wrote:

Systemverilog does have some built-in simulation features that
I had to write code to cover in vhdl.
However it is but mostly a game of catch-up.
Most of the "new" sv language features have
been covered by [VHDL] tools for ten years.

-- Mike Treseler

Mike,

SystemVerilog adds a huge amount of functionality that VHDL does not
have. Whilst I have no interest in promoting one language over
another, it is important that readers unfamiliar with the languages
are not given the wrong impression. The following brief list
demonstates just some of the features that I mean:

* Object-oriented programming
* Constrained random stimulus generation
* Functional coverage monitoring constructs
* Assertions (although PSL now provides this for VHDL)

Mark

 

[mjl296@hotmail.com]

On 13 Oct, 08:16, e2po...@yahoo.com wrote:

That said, you must not forget that plenty of big chips are still
verified using vanilla Verilog and VHDL. Many companies are still only
beginning to look at SystemVerilog and SystemC, and have been
producing successful products without these tools for years.
are stuck with free tools, you may find that this is your best
approach.

do the companies seriously consider system verilog approaches?

Yes. Take a look at the Verification Guild to get a feel for the
uptake. http://verificationguild.com/

You could consider using C/C++ or another software language
to create test vectors that you then play through the DUT using
Verilog.

how do we do that? do i need to have a compiler which support both c++
and verilog
OR we use facilities provided by verilog for c interfacing?

What I meant was, write a software program (in C or whatever you like)
that calculates values for your circuits inputs and expected outputs.
Write these values into files that can be read into a Verilog
simulation. You can then run your software to produce the files before
the simulation. All the Verilog testbench need do is somehow play the
file contents into your circuit, monitor its responses and produce an
error if they do not match the expected values that you generated.
This approach does not need a special C compiler, or use the PLI to
link to Verilog.

I caution you that this approach is not perfect. You may spend a lot
of time trying to align the circuits outputs with those in the files,
for example. Also, the file sets quickly get huge. However, this is a
simple and powerful technique.

what is i start learning vhdl instead? how does vhdl compare with
systemverilog?

There are many people who have strong feelings about which language is
better, VHDL or Verilog. One thing I can probably safely say is that
the two languages serve roughly the same purpose. If you are finding
that Verilog is failing to meet your verification needs, then you will
most likely have similar problems with VHDL. SystemVerilog provides
many verification features that are not present in either Verilog or
VHDL. We are starting to use SystemVerilog to verify VHDL designs as
well as Verilog ones.

 

[mjl296@hotmail.com]

On 12 Oct, 14:29, "HT-Lab" <han...@ht-lab.com> wrote:

mjl...@hotmail.com> wrote in message
In theory it is possible to write SystemC at the RTL level, and you
could simulate this with any C++ compiler. However, you won't find a
synthesis tool that accepts it, so it is of little use.

There are a number of SystemC synthesis tools available ranging from the
low'ish cost SystemCrafters up to $$$ ForteDS. There is also a SystemC
Synthesis standard draft.

Hanswww.ht-lab.com

My mistake - Thanks Hans.

 

[Mike Treseler]

mjl296@hotmail.com wrote:

Whilst I have no interest in promoting one language over
another ...

I'm sure that is true,
however an anonymous posting
does little to inspire my confidence.

it is important that readers unfamiliar with the languages
are not given the wrong impression. The following brief list
demonstates just some of the features that I mean:

* Object-oriented programming
* Constrained random stimulus generation
* Functional coverage monitoring constructs
* Assertions (although PSL now provides this for VHDL)

The original poster asked about
a complex synthesis project.
Which of the features above are applicable to
synthesis, and of those, which are
working in synthesis tools available today?

-- Mike Treseler

 

[Evan Lavelle]

On Sun, 14 Oct 2007 14:49:10 -0000, "mjl296@hotmail.com"
<mjl296@hotmail.com> wrote:

SystemVerilog adds a huge amount of functionality that VHDL does not
have. Whilst I have no interest in promoting one language over
another, it is important that readers unfamiliar with the languages
are not given the wrong impression. The following brief list
demonstates just some of the features that I mean:

* Object-oriented programming
* Constrained random stimulus generation
* Functional coverage monitoring constructs
* Assertions (although PSL now provides this for VHDL)

And, of course, 'e' had all this 10 years before SystemVerilog
existed. It also has the advantage of a clean syntax that doesn't
suffer from several generations of incompatible fixes and extensions.

Evan

 

[EdA]

On Oct 15, 5:29 pm, Evan Lavelle <nos...@nospam.com> wrote:

On Sun, 14 Oct 2007 14:49:10 -0000, "mjl...@hotmail.com"

mjl...@hotmail.com> wrote:
SystemVerilog adds a huge amount of functionality that VHDL does not
have. Whilst I have no interest in promoting one language over
another, it is important that readers unfamiliar with the languages
are not given the wrong impression. The following brief list
demonstates just some of the features that I mean:

* Object-oriented programming
* Constrained random stimulus generation
* Functional coverage monitoring constructs
* Assertions (although PSL now provides this for VHDL)

And, of course, 'e' had all this 10 years before SystemVerilog
existed. It also has the advantage of a clean syntax that doesn't
suffer from several generations of incompatible fixes and extensions.

Sorry to join the conversation late...

Clean syntax example 1:

for {i = 0; i < 10; i += 1} {
};

Clean syntax example 2:

val = config.as_a(FOO bar_intf_config_s).field;

Clean syntax example 3:

keep agent is a FOOBAR frotz_agent_u (fred) => fred.name == name;

etc etc etc

Right, 'e' just suffers from several generation of incompatible in-
bred fixes and extensions:

*** Warning: DEPR_DIRECTIVE_IN_CONSTRAINT:
Non-Boolean constraints are not supported within compound
constraints.
This was allowed in previous versions but is currently under
deprecation.

*** Warning: DEPR_RESERVED_KEYWORD:
The keyword 'print|item|sequence|start|...' is used as an
identifier.
This was allowed in previous versions and is currently under
deprecation.

But I digress...

/Ed

 

[Evan Lavelle]

On Tue, 16 Oct 2007 13:43:44 -0000, EdA <ed.arthur@gmail.com> wrote:

Clean syntax example 1:

for {i = 0; i < 10; i += 1} {
};

If you want C-style syntax, then e's probably the wrong language. If
not, you might prefer

for i from 1 to 10 {...};

Clean syntax example 2:

val = config.as_a(FOO bar_intf_config_s).field;

Clean syntax example 3:

keep agent is a FOOBAR frotz_agent_u (fred) => fred.name == name;

etc etc etc

Seems clear enough to me. Can't really comment without seeing the
SystemVerilog equivalent.

Right, 'e' just suffers from several generation of incompatible in-
bred fixes and extensions:

*** Warning: DEPR_DIRECTIVE_IN_CONSTRAINT:
Non-Boolean constraints are not supported within compound
constraints.
This was allowed in previous versions but is currently under
deprecation.

*** Warning: DEPR_RESERVED_KEYWORD:
The keyword 'print|item|sequence|start|...' is used as an
identifier.
This was allowed in previous versions and is currently under
deprecation.

You're kidding, right?

I learnt 'e' in 2 weeks on the job. It's next to impossible to learn
Verilog in 2 weeks, let alone SystemVerilog. My point was that any
code which is "SystemVerilog" has gone through several generations
including early XL, XL 1.6, V-95, V-2001, V-2005, and "SystemVerilog".
At the start of this range we don't even have non-blocking
assignments. Your first example included "i += 1". Can't do that in
Verilog; assignments aren't expressions. I presume you can do that in
SystemVerilog, though. Seems like a rather fundamental change in
expression syntax to me. What about all the simple stuff - loop
breaks, loop continues, function returns? If you know how, you can
bodge up a continue or a break in Verilog. You may even be able to
bodge up a return that works, but the general case is not trivial. You
won't manage a recursive routine, even in 2001/2005. Presumably
SystemVerilog fixes this lot. What about the pseudo-type system of
Verilog? I understand that SystemVerilog has fixed much of that. you
can't get any more fundamental than reconstructing a type system. If
that lot, and all the rest of it, doesn't amount to "several
generations of incompatible fixes and extensions", then what on earth
does?

Evan

 

[EdA]

On Oct 16, 5:41 pm, Evan Lavelle <nos...@nospam.com> wrote:

On Tue, 16 Oct 2007 13:43:44 -0000, EdA <ed.art...@gmail.com> wrote:
Clean syntax example 1:

for {i = 0; i < 10; i += 1} {
};

If you want C-style syntax, then e's probably the wrong language. If
not, you might prefer

for i from 1 to 10 {...};



Clean syntax example 2:

val = config.as_a(FOO bar_intf_config_s).field;

Clean syntax example 3:

keep agent is a FOOBAR frotz_agent_u (fred) => fred.name == name;

etc etc etc

Seems clear enough to me. Can't really comment without seeing the
SystemVerilog equivalent.



Right, 'e' just suffers from several generation of incompatible in-
bred fixes and extensions:

*** Warning: DEPR_DIRECTIVE_IN_CONSTRAINT:
Non-Boolean constraints are not supported within compound
constraints.
This was allowed in previous versions but is currently under
deprecation.

*** Warning: DEPR_RESERVED_KEYWORD:
The keyword 'print|item|sequence|start|...' is used as an
identifier.
This was allowed in previous versions and is currently under
deprecation.

You're kidding, right?

I learnt 'e' in 2 weeks on the job. It's next to impossible to learn
Verilog in 2 weeks, let alone SystemVerilog. My point was that any
code which is "SystemVerilog" has gone through several generations
including early XL, XL 1.6, V-95, V-2001, V-2005, and "SystemVerilog".
At the start of this range we don't even have non-blocking
assignments. Your first example included "i += 1". Can't do that in
Verilog; assignments aren't expressions. I presume you can do that in
SystemVerilog, though. Seems like a rather fundamental change in
expression syntax to me. What about all the simple stuff - loop
breaks, loop continues, function returns? If you know how, you can
bodge up a continue or a break in Verilog. You may even be able to
bodge up a return that works, but the general case is not trivial. You
won't manage a recursive routine, even in 2001/2005. Presumably
SystemVerilog fixes this lot. What about the pseudo-type system of
Verilog? I understand that SystemVerilog has fixed much of that. you
can't get any more fundamental than reconstructing a type system. If
that lot, and all the rest of it, doesn't amount to "several
generations of incompatible fixes and extensions", then what on earth
does?

Evan,

My message was done somewhat tongue-in-cheek. As we know no
programming
language is perfect (my favorite one is awk, which falls short in many
many
categories obviously, let's not even go there) and we live in an
imperfect world.
Quoting Janick Bergeron, my favorite language is the one I'm NOT
presently
using.

/Ed