SystemC to Verilog translator

[Javier Castillo]

Hello:

I am looking for a free SystemC to Verilog translator. Anybody knows one?

Regards

Javier Castillo
jcastillo@opensocdesign.com

 

[Russell Fredrickson]

Hi Javier,

Well -- it depends on what your SystemC looks like. Generally a SystemC
to Verilog transformation would be thought as a synthesis step because
generally you are translating from a higher level of abstraction (behaviroal
SystemC) to a lower-level of abstraction (Verilog RTL). This is generally
thought to be a hard problem -- though there are several solutions out there
that are just coming to market (though some take C and not SystemC). Though
my understanding is that for those that do support SystemC -- only a certain
subset of the language is supported for synthesis (much like Verilog
synthesis).

One free tool I know of is Spark, but it takes only C as input, (
http://mesl.ucsd.edu/spark/ ) . Of course probably the closest fit to
SystemC to Verilog synthesis (though you would have to pay $$) is what Forte
offers ( http://www.forteds.com ) -- though there are other companies like
Synfora ( http://www.synfora.com/ ) and probably others (I'm sure if you did
a search on the DAC web page you might be able to come up with some others).
A google search on using keywords 'SystemC to Verilog' also seems to provide
interesting results

Though I suppose if the SystemC was written at the lower-level
RTL-level, one could probably come up with more of a translator to Verilog
RTL without too much trouble. However, using SystemC to write an RTL-level
description is generally thought to be a bad idea since Verilog is much more
suited to that task.

Hope that helps,
Russell

"Javier Castillo" <jcastillo@opensocdesign.com> wrote in message
news:Xns954F8152239A2jcastilloopensocdesi@193.147.184.15...

Hello:

I am looking for a free SystemC to Verilog translator. Anybody knows
one?

Regards

Javier Castillo
jcastillo@opensocdesign.com