System Verilog

[nivparsons]

I'm just starting to use SV Assertions with my VHDL code in Questa.
Is there a group that supports this kind of thing? TheSystem Verilog group I found seems unused?

Regards, Niv.

 

[HT-Lab]

On 14/03/2013 18:43, nivparsons wrote:

I'm just starting to use SV Assertions with my VHDL code in Questa.
Is there a group that supports this kind of thing? TheSystem Verilog group I found seems unused?

Regards, Niv.

I would try the Verification Guild:

http://verificationguild.com/

Hans
www.ht-lab.com