System Verilog & the VHDL user

[Niv]

Hi all, we currently use VHDL for all our design & verification via
testbenches.
I have been asked to look at alternative verification methodologies,
particularly SystemVerilog.

(I've been on a PSL course a few years ago, but until now never had
the tool(s) to exploit it's use, but
people seem to think SysVerilog may be a better approach anyway.

So, what is the best book(s) to learn SV for a VHDL conversant
audience, and possibly more important,
whare can we quickly learn what SV can do for us above and beyond VHDl
testbenches.

(Cross posted to Verilog group)

Regards, Niv.

 

[Dal]

Approaching a similar decision myself. Have you considered SystemC?

I would also like to know what SV can do above and beyond SC and VHDL.

Darrin

 

[Mike Treseler]

On 16 Apr, 12:47, "HT-Lab" <hans...@ht-lab.com> wrote:
SystemVerilog is a language, not a verification methodology. Perhaps you
should focus on the required methodology first and then look at the
available languages and tools?

Exactly.

Niv wrote:

We do have ModelSim SE & Questa, so that's not an issue.
However, no-one is really using Questa at the moment due to lack of
understanding of what we can do with it.

You may be able to do what you need with plain vhdl.
Make sure the testbench stim and response data is properly synchronized.
Use STA to verify timing, not the testbench.
Make a synchronous watcher process for global/mulicycle assertions.

We want to address our verification methodology to make it more
thorough & hopefully simpler, albeit having to learn SV on top of
VHDL. (Why no SystemVHDL?)

I agree with Hans.
Focus on what is missing in your existing testbench suites.
You may or may not need a new language.

-- Mike Treseler

 

[Niv]

On 16 Apr, 12:47, "HT-Lab" <han...@ht-lab.com> wrote:

"Niv" <kev.pars...@mbda.co.uk> wrote in message

news:24b1ea6c-6194-49c8-94eb-2746fd2c25e3@t54g2000hsg.googlegroups.com...

Hi all, we currently use VHDL for all our design & verification via
testbenches.
I have been asked to look at alternative verification methodologies,
particularly SystemVerilog.

SystemVerilog is a language, not a verification methodology. Perhaps you
should focus on the required methodology first and then look at the
available languages and tools?



(I've been on a PSL course a few years ago, but until now never had
the tool(s) to exploit it's use,

Yes unfortunately the tools for PSL/SVA are quite expensive, lets hope
VHDL2007/8 will introduce more people to the power of assertions and as such
bring the price down.

but
people seem to think SysVerilog may be a better approach anyway.

Better approach for what, Assertion Based Verification(ABV), Testbench
Development, Constrained Random(CR), Transaction Level Modelling(TLM),
fixed/floating point modelling?

So, what is the best book(s) to learn SV for a VHDL conversant
audience, and possibly more important,
whare can we quickly learn what SV can do for us above and beyond VHDl
testbenches.

Probably less than what you would expect. As posted some time ago VHDL can
be used for TLM, CR, ABV (using PSL) but probably not as easy as with a
modern language like SystemVerilog/SystemC.

Another option as suggested by Darrin is to look at SystemC. The advantage
of SystemC is that you can add it to a "lowcost" simulator like Modelsim PE
(no need to go to SE/Questa) and it will give you access to TLM, CR, OO and
a very easy C/C++ interface to your PE VHDL.

Hanswww.ht-lab.com





(Cross posted to Verilog group)

Regards, Niv.- Hide quoted text -

- Show quoted text -

We do have ModelSim SE & Questa, so that's not an issue.
However, no-one is really using Questa at the moment due to lack of
understanding of what we can do with it.

We currently do large FPGA designs and test using VHDL testbenches
(quite a lot of VHDL ASSERT statements are used).
I've been led to believe (possibly erroneously) that with
SystemVeilog, the assertions are more comprehensive & simpler to
apply.
I realise that SV is a language & not a methodology; and there seems a
general consensus here that SV will "win" over SystemC;
although that could be rubbish.

We want to address our verification methodology to make it more
thorough & hopefully simpler, albeit having to learn SV on top of
VHDL. (Why no SystemVHDL?)

Niv.

 

[Jim Lewis]

Niv,

We want to address our verification methodology to make it more
thorough & hopefully simpler, albeit having to learn SV on top of
VHDL. (Why no SystemVHDL?)

Why no SystemVHDL?

The VHDL standards group has proposals for OO (an extension
to the existing protected types) and randomization. What we
need is more user participation both expressing the need for
these features and helping fund the LRM editing. Interested,
send me email?



WRT, Han's list of verification tasks:
Assertion Based Verification(ABV):
Re-iterating Han's statement, PSL has been integrated into VHDL 2008.

Transaction Level Modelling(TLM):
Using records with resolved elements, this is a very easy thing
to do. Perhaps easier than the current methodology being used
in SV as it uses traditional entities rather than OO constructs.
Entities provide concurrency naturally, with OO methods, you need
to manually fork your processes.

Testbench Development:
With VHDL you use a traditional entity based - just like HDL.

Constrained Random(CR):
Simple constraints are straight forward to do procedurally.
I will have more on this in the verification book I am working on.
It is available now in our training classes: http://www.synthworks.com

fixed/floating point modelling:
This is something that is supported with VHDL packages (2008),
and probably missing in Verilog.

Cheers,
Jim
SynthWorks VHDL Training
IEEE 1076 WG chair