System Verilog:-streaming operator

[varsha]

Guys,Any idea on what is streaming operator?And how is it diffferent
from static casting operator?

 

[Jonathan Bromley]

On Thu, 26 Feb 2009 17:49:56 -0800 (PST), varsha wrote:

Guys,Any idea on what is streaming operator?
And how is it diffferent from static casting operator?

Do you mean the streaming concatenation operator {<<{}}
in SystemVerilog? This operator does several rather
unusual things:
- it allows you to assemble a stream of bits, of
arbitrarty length, from almost any collection of
expressions - including unpacked arrays and
structs, and the contents of class objects;
- then, if you use << right-to-left streaming, it
reverses that stream of bits - but it does so
in "chunks" or blocks of a size you specify;
- finally, the resulting stream of bits can be
copied into any reasonable target variable -
for example, an unpacked array, a queue, ...
and the ordering of the bits in that copy is
defined.
- and, as a final trick, it can appear as the
TARGET of an assignment, in which case it
does the reverse operation, unpacking a stream
of bits into a collection of variables.

A few simple examples:

// in these variable-names, each letter
// stands for one bit
bit a,b,c,d;
bit [3:0] efgh;
bit [7:0] pqrstuvw;

// another variable:
bit [7:0] x;

// example 1: assemble a bunch of bits
// using left-to-right streaming
x = {>>{a,b,c,d,efgh}};
// yields x = abcdefgh

// example 2: reverse a vector using right-to-left
// streaming with the default block size of 1 bit
x = {<<{pqrstuvw}};
// yields x = wvutsrqp

// example 3: reverse a vector using right-to-left
// streaming with block size = 4
x = {<<4{pqrstuvw}};
// yields x = tuvwpqrs

// example 4: unpack (streaming concatenation as target)
{>>{a,b,c,d,efgh}} = pqrstuvw;
// yields a=p, b=q, c=r, d=s, efgh=tuvw

I don't know the current state of synthesis support for
this construct; all the examples I gave above *should*
be synthesisable, but I haven't tried it in real tools.

Hope this helps
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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On Thursday, February 26, 2009 5:49:56 PM UTC-8, varsha wrote:

Guys,Any idea on what is streaming operator?And how is it diffferent
from static casting operator?

Just to explain the other half. casting operator (i.e. ') is used while assigning a pattern.

bit [2:0] vec_pack;
bit vec_unpack [2:0];

vec_unpack = '{vec_pack[2], vec_pack[1], vec_pack[0]};

they same can be achieved using left-to-right streaming operator, believe is simulator dependant.
{>>{vec_unpack} = vec_pack;