system verilog simulator?

i've started learning systemverilog and suprised by the support given
for testbench writing. however i am unable to find a simulator which
is available free or at least a demo version. Therefore i had to move
to verilog again and currently trying to find good resources on
verilog testbench writing hopefully with lot of examples and projects.
Can some one point to a good resource and if possible mention a free
or demo version of a systemverilog simulatior.

 

[Charles, NG]

If you are a student (or can convince them that they should regard you
as as one) I'd take a look at Aldec ActiveHDL (http://www.aldec.com).

A while back they introduced a program giving students a license for six
months or a year (I've forgotten which). It's a mixed language
VHDL/Verilog/SystemVerilog/SystemC simulator. The SystemVerilog
implementation isn't perfect yet but at least in their PRO Tool
(Riviera) it's quite usable, as long as you can get by without
complicated things in classes. As far as I know both ActiveHDL and
Riviera use a common kernel.

Hope this helps,

Charles

 

On Oct 9, 7:46 pm, "Charles, NG" <site_blackh...@trellisys.ie> wrote:

If you are a student (or can convince them that they should regard you
as as one) I'd take a look at Aldec ActiveHDL (http://www.aldec.com).

A while back they introduced a program giving students a license for six
months or a year (I've forgotten which). It's a mixed language
VHDL/Verilog/SystemVerilog/SystemC simulator. The SystemVerilog
implementation isn't perfect yet but at least in their PRO Tool
(Riviera) it's quite usable, as long as you can get by without
complicated things in classes. As far as I know both ActiveHDL and
Riviera use a common kernel.

Hope this helps,

Charles

thank you very much for the info.
apart from that, i downloaded ModelSim XE III/Starter 6.2g version
from xilinx. This seems to support systemverilog compilation, but im
unable to do simulatio
because of the following error.

Fatal: Bad library format, library not compiled with XE compiler.

please let me know if you know the solution to this.

 

[Systemv User]

When I evaluated Aldec Active-HDL 7.2sp2, their Systemverilog support
was behind Mentor/Synopsys (and even Cadence!)

The lowest price option for Systemverilog compilation used to be
Modelsim PE Student Edition (6.3p1 or older), but Mentor removed
Systemverilog simulation entirely from the free PE Student Edition.
(Funny, you can still *compile* .sv files without error, and the 'sysvlog'
technotes
are still in the help-menu... but a snapshot containing any
systemverilog hierarchy refuses to run.)

Cadence Incisive and Synopsys VCS are definitely priced for the 'enterprise'
level
(i.e. not for direct individual/end-user purchase.)

That leaves Aldec Active-HDL and Mentor Modelsim PE as the contendors in the
<$6000 USD category. I think both Aldec and Mentor have special
"desktop" editions of their respective products... at the $3000-4000 level.
Active-HDL has a lot more bells & whistles. But personally, Mentor's
simulator-engine is more robust. At least it supported a lot more
Systemverilog
syntax than Active-HDL 7.2sp2.

Even simple things like this triggered syntax-errors in Active-HDL:
module top;
// (Note I just typed this up without testing it...)
`define MAKE_MACRO( x ) MACRO_``x
`define MAKE_TEXT_MACRO( x ) `"TEXT_``MACRO`"

initial begin : my_main
$display( "abcd = '%0s'", `MAKE_TEXT_MACRO( 1234 ) );
end : my_main

endmodule : top

"Charles, NG" <site_blackhole@trellisys.ie> wrote in message
news:fegeq5$71m$1@daniel-new.mch.sbs.de...

If you are a student (or can convince them that they should regard you
as as one) I'd take a look at Aldec ActiveHDL (http://www.aldec.com).

A while back they introduced a program giving students a license for six
months or a year (I've forgotten which). It's a mixed language
VHDL/Verilog/SystemVerilog/SystemC simulator. The SystemVerilog
implementation isn't perfect yet but at least in their PRO Tool
(Riviera) it's quite usable, as long as you can get by without
complicated things in classes. As far as I know both ActiveHDL and
Riviera use a common kernel.

Hope this helps,

Charles