System Verilog Questions

I have a few system verilog questions that I was hoping someone might
be able to answer:

(1) Is it legal (syntactically i mean, as opposed to allowed by any
given simulator) to reference a signal in a clocking block as a
functional coverage point: in particular, is something like this legal:

interface itfc();
clocking cb @(posedge clk);
input sig = <hierarchical name>;
endclocking
endinterface

module mod(itfc i);
covergroup cg @(i.cb);
coverpoint i.cb.sig;
endgroup
endmodule

(2) in the example module above, does cg need to be instantiated
somewhere with new()?

Any insight will be greatly appreciated.

 

[Ajeetha]

Hi,
Answers to both your questions is yes, LRM says both.

Here is a working example, derived from yours.

HTH
Ajeetha, CVC
www.noveldv.com

interface itfc(input logic clk);
clocking cb @(posedge clk);
input sig = top.my_sig;
endclocking
modport my_mp (clocking cb);
endinterface

module mod(itfc i);
covergroup cg @(i.cb);
coverpoint i.cb.sig;
endgroup

cg cg_0;

initial
cg_0 = new();
endmodule

module top;
logic my_sig, clk = 0;
itfc i (.*);
mod mod_0 (.*);
endmodule : top

 

[Enchanter]

Does VCS 2005.09 support the covergroup function?


Ajeetha wrote:

Hi,
Answers to both your questions is yes, LRM says both.

Here is a working example, derived from yours.

HTH
Ajeetha, CVC
www.noveldv.com

interface itfc(input logic clk);
clocking cb @(posedge clk);
input sig = top.my_sig;
endclocking
modport my_mp (clocking cb);
endinterface

module mod(itfc i);
covergroup cg @(i.cb);
coverpoint i.cb.sig;
endgroup

cg cg_0;

initial
cg_0 = new();
endmodule

module top;
logic my_sig, clk = 0;
itfc i (.*);
mod mod_0 (.*);
endmodule : top

 

[katelman@gmail.com]

Thanks for the help, I appreciate it. Believe it or not, I have read
the relevant parts of the LRM quite carefully, but my (unnamed)
simulator appears to be very finicky and in fact gives an internal
error on the code that you wrote below.

As a side note, do you find the syntax of covergroup instantiation to
be strange? I would have expected something like

cg cg_0();

rather than being treated as a class by having to call new.

Ajeetha wrote:

Hi,
Answers to both your questions is yes, LRM says both.

Here is a working example, derived from yours.

HTH
Ajeetha, CVC
www.noveldv.com

interface itfc(input logic clk);
clocking cb @(posedge clk);
input sig = top.my_sig;
endclocking
modport my_mp (clocking cb);
endinterface

module mod(itfc i);
covergroup cg @(i.cb);
coverpoint i.cb.sig;
endgroup

cg cg_0;

initial
cg_0 = new();
endmodule

module top;
logic my_sig, clk = 0;
itfc i (.*);
mod mod_0 (.*);
endmodule : top

 

[Ajeetha]

Hi,

As a side note, do you find the syntax of covergroup instantiation to
be strange? I would have expected something like

cg cg_0();

rather than being treated as a class by having to call new.

Well, I believe this is a side effect of a HDVL, this is derived from
Vera style. In SVTB context, cg can be inside classes and since classes
(instances) are dynamically constructed using new() so are cg. Now, cg
can be used inside module as well, hence new() them as well!

That's just my rationale.

Regards
Ajeetha, CVC
www.noveldv.com