A
Andy Luotto
Guest
I am designing an interface to model an asynchronous I/F with bidi bus
and ALE like
interface xram_if
(output CLK, nRST);
timeunit 1ns;
timeprecision 1ps;
logic [7:0] AD;
logic ALE;
logic nWR;
logic nRD;
modport master (
output nWR,
output nRD,
output ALE,
inout AD,
import write,
import read
);
modport slave (
input nWR,
input nRD,
input ALE,
inout AD
);
logic clk;
logic nrst;
logic [7:0] adin;
logic [7:0] adout;
assign CLK = clk;
assign nRST = nrst;
////////////////////////////////////////////////////////////////////////////////
// set idel values to the master interface outputs and generate a
reset shot
////////////////////////////////////////////////////////////////////////////////
task init ();
begin
ALE = 0;
nRD = 1;
nWR = 1;
AD = `DATAW'bz;
nrst = 1'b1;
#1;
nrst = 1'b0;
repeat (`RESET_LEN) @(negedge CLK);
nrst = 1'b1;
end
endtask // init
////////////////////////////////////////////////////////////////////////////////
// see section 27 of
// http://www.atmel.com/dyn/resources/prod_documents/doc2487.pdf
////////////////////////////////////////////////////////////////////////////////
task write (
input t_xram_addr addr,
input t_xram_data data
);
begin
....
end
endtask // write
task read (
input t_xram_addr addr,
output t_xram_data data
);
begin
....
end
endtask
I want to instantiate it in a test bench, e.g.
xram_if xramif (
.CLK(MCLK),
.nRST(nRST)
);
and I need a master interface to drive my DUT (so there are modports
above)
My DUT does not support interfaces (it is Verilog 2001)
How do I specifiy
- which interface flavor (master or slave)
How doi I connect my interface to the DUT?
The following does not work ...
I think I am missing sopme big points here ...
vdt_top i_vdt_top(
....
.access_if_ale_i (xramif.master.ALE),
.access_if_nwr_i (xramif.master.nWR),
.access_if_nrd_i (xramif.master.nRD),
.....
.access_if_ad_0 (xramif.master.AD[0]),
.access_if_ad_1 (xramif.master.AD[1]),
.access_if_ad_2 (xramif.master.AD[2]),
.access_if_ad_3 (xramif.master.AD[3]),
.access_if_ad_4 (xramif.master.AD[4]),
.access_if_ad_5 (xramif.master.AD[5]),
.access_if_ad_6 (xramif.master.AD[6]),
.access_if_ad_7 (xramif.master.AD[7]),
);
Thanks to whoever will help
cheers
and ALE like
interface xram_if
(output CLK, nRST);
timeunit 1ns;
timeprecision 1ps;
logic [7:0] AD;
logic ALE;
logic nWR;
logic nRD;
modport master (
output nWR,
output nRD,
output ALE,
inout AD,
import write,
import read
);
modport slave (
input nWR,
input nRD,
input ALE,
inout AD
);
logic clk;
logic nrst;
logic [7:0] adin;
logic [7:0] adout;
assign CLK = clk;
assign nRST = nrst;
////////////////////////////////////////////////////////////////////////////////
// set idel values to the master interface outputs and generate a
reset shot
////////////////////////////////////////////////////////////////////////////////
task init ();
begin
ALE = 0;
nRD = 1;
nWR = 1;
AD = `DATAW'bz;
nrst = 1'b1;
#1;
nrst = 1'b0;
repeat (`RESET_LEN) @(negedge CLK);
nrst = 1'b1;
end
endtask // init
////////////////////////////////////////////////////////////////////////////////
// see section 27 of
// http://www.atmel.com/dyn/resources/prod_documents/doc2487.pdf
////////////////////////////////////////////////////////////////////////////////
task write (
input t_xram_addr addr,
input t_xram_data data
);
begin
....
end
endtask // write
task read (
input t_xram_addr addr,
output t_xram_data data
);
begin
....
end
endtask
I want to instantiate it in a test bench, e.g.
xram_if xramif (
.CLK(MCLK),
.nRST(nRST)
);
and I need a master interface to drive my DUT (so there are modports
above)
My DUT does not support interfaces (it is Verilog 2001)
How do I specifiy
- which interface flavor (master or slave)
How doi I connect my interface to the DUT?
The following does not work ...
I think I am missing sopme big points here ...
vdt_top i_vdt_top(
....
.access_if_ale_i (xramif.master.ALE),
.access_if_nwr_i (xramif.master.nWR),
.access_if_nrd_i (xramif.master.nRD),
.....
.access_if_ad_0 (xramif.master.AD[0]),
.access_if_ad_1 (xramif.master.AD[1]),
.access_if_ad_2 (xramif.master.AD[2]),
.access_if_ad_3 (xramif.master.AD[3]),
.access_if_ad_4 (xramif.master.AD[4]),
.access_if_ad_5 (xramif.master.AD[5]),
.access_if_ad_6 (xramif.master.AD[6]),
.access_if_ad_7 (xramif.master.AD[7]),
);
Thanks to whoever will help
cheers