System Verilog packed <-> unpacked

Hi,

Does anyone know what is the simplest
way to convert packed to unpacked arrays
(or should I never want to do this)?
For instance, if I had:

reg [7:0] bytes [3:0];
reg [31:0] word;

...
for(i=0;i&lt;3;i++)
bytes = word[8*i+7:8*i];
...

The word[8*i+7:8*i] gives an error:
Cannot evaluate the expression
((8 * i) + 7)

or word[7+:8*i] gives
The following expression should be a constant.
Expression: (8 * i)

I used to solve this using the Verilog-2001
generate, but it's a nuisance to introduce
it everywhere I need it. Also, it seems kind
of silly to have this limitation for verification.

Regards,
e

 

[gtwrek@pacbell.net]

On Aug 10, 9:55 am, easchei...@yahoo.com wrote:

Does anyone know what is the simplest
way to convert packed to unpacked arrays
(or should I never want to do this)?
For instance, if I had:

reg [7:0] bytes [3:0];
reg [31:0] word;

Well, you SHOULD never want to do this as using packed
arrays make this so much easier, and this is exactly
what it's meant for.

reg [ 3 : 0 ][ 7 : 0 ] bytes;
reg [ 31 : 0] word;
always @*
bytes = word;

Simple, neat, compact.

I don't think there's *ANY* case where something could have forced
you to make "bytes" unpacked. I think everywhere you could use an
UNPACKED array, you could use a PACKED array instead. (The reverse
is NOT true.)

In any case, if you still want to do it, here's how I would:

....
always @*
begin
for( i = 0; i &lt; 4; i++ )
bytes[ i ] = word &gt;&gt; ( 4'd8 * i );
end

You could do it with generate. Or use the "Verilog-2001" constant
width, variable range
expression:

for( i = 0; i &lt; 4; i++ )
bytes[ i ] = word[ ( ( 4'd8 * i ) + 7 ) -: 8 ];

I think the above's right - didn't test it however. Still messy.

The error message you got is because of the non-constant range
expression.
Verilog-1995 must have a static, elaboration time memory footprint.
So all ranges must be staticcally sized. Now, in your expression
the range is a variable, but the WIDTH is always constant (8).
However,
it could be difficult for tools to recognize the constant width.
Hence the
verilog-2001 part-select feature above.

Regards,

Mark

 

On Aug 10, 1:47 pm, "gtw...@pacbell.net" &lt;gtw...@pacbell.net&gt; wrote:

I don't think there's *ANY* case where something could have forced
you to make "bytes" unpacked. I think everywhere you could use an
UNPACKED array, you could use a PACKED array instead.

Not quite, though this may not always be clearly specified.

For example, you can pass an element of an unpacked array to a task/
function by reference. You shouldn't expect that to work for an
element of a packed array.

I think some of the "built-in methods" for arrays can only be applied
to unpacked arrays also.

;

This can be simplified to

bytes = word[8*i +: 8];

An indexed part select will let you specify the lower bound as the
starting point even when the range was declared high:low, and will use
it as the left or right bound of the part select, whichever is
correct.