System Verilog: multiplexing an array of interfaces

I need a MUX that from an array of input interfaces has in output the interface of the array indicated from the two MSB of an address bus.
the number of interfaces of the array is a parameter: pNUM_IF.

interface my_if;
wire a;
wire b;
endinterface // my_if


parameter pNUM_IF= 4;
parameter pADDRESS_WIDTH=8;
parameter pDECODE_BITS=2;

module MUX
(
my_if if_BUS [pNUM_IF-1:0] ,
my_if out,
input [pADDRESS_WIDTH-1:0] iADDRESS
);

genvar i;

generate
for ( i=0;i<pNUM_IF-1;i++)
begin : genloop
always
begin

if(i==iADDRESS[pADDRESS_WIDTH-1 -: pDECODE_BITS])
begin
out=if_BUS;
end
end

end
endgenerate


endmodule


____________

Modelsim gives me an error I don't understand:

# ** Error: MUX_int.v(33): 'out' is not a variable
# ** Error: MUX_int.v(33): Illegal LHS of assignment.

can someone help me?
Thank you in advance

 

[Mark Curry]

In article <1fb45c2c-03dc-448c-a6e1-6ec8aa5909ca@googlegroups.com>,
<fabio.malatesta27@gmail.com> wrote:

I need a MUX that from an array of input interfaces has in output the interface of the array indicated from the two MSB of an address bus.
the number of interfaces of the array is a parameter: pNUM_IF.

interface my_if;
wire a;
wire b;
endinterface // my_if


parameter pNUM_IF= 4;
parameter pADDRESS_WIDTH=8;
parameter pDECODE_BITS=2;

module MUX
(
my_if if_BUS [pNUM_IF-1:0] ,
my_if out,
input [pADDRESS_WIDTH-1:0] iADDRESS
);

genvar i;

generate
for ( i=0;i<pNUM_IF-1;i++)
begin : genloop
always
begin

if(i==iADDRESS[pADDRESS_WIDTH-1 -: pDECODE_BITS])
begin
out=if_BUS;
end
end

end
endgenerate


endmodule

Fabio,

Interfaces are (either explicity or implicity, I'm not sure which) like NET data types.
You need to assign them continously, not with a procedure.

Try changing it to a generate if() clause instead, and use an assign.

Something like

genvar i;
generate
for( i=0;i<pNUM_IF-1;i++ )
begin : genloop
if( i == blah )
begin : gen_mux
assign out = if_BUS[ i ];
end
end
endgenerate

I'm fairly sure some variant of the above should get you there.

Regards,

Mark

 

Il giorno mercoledě 8 aprile 2015 21:06:06 UTC+2, Mark Curry ha scritto:

In article <1fb45c2c-03dc-448c-a6e1-6ec8aa5909ca@googlegroups.com>,
fabio.malatesta27@gmail.com> wrote:
I need a MUX that from an array of input interfaces has in output the interface of the array indicated from the two MSB of an address bus.
the number of interfaces of the array is a parameter: pNUM_IF.

interface my_if;
wire a;
wire b;
endinterface // my_if


parameter pNUM_IF= 4;
parameter pADDRESS_WIDTH=8;
parameter pDECODE_BITS=2;

module MUX
(
my_if if_BUS [pNUM_IF-1:0] ,
my_if out,
input [pADDRESS_WIDTH-1:0] iADDRESS
);

genvar i;

generate
for ( i=0;i<pNUM_IF-1;i++)
begin : genloop
always
begin

if(i==iADDRESS[pADDRESS_WIDTH-1 -: pDECODE_BITS])
begin
out=if_BUS;
end
end

end
endgenerate


endmodule

Fabio,

Interfaces are (either explicity or implicity, I'm not sure which) like NET data types.
You need to assign them continously, not with a procedure.

Try changing it to a generate if() clause instead, and use an assign.

Something like

genvar i;
generate
for( i=0;i<pNUM_IF-1;i++ )
begin : genloop
if( i == blah )
begin : gen_mux
assign out = if_BUS[ i ];
end
end
endgenerate

I'm fairly sure some variant of the above should get you there.

Regards,

Mark

Hi Mark,
I really thank you for your help but with this code

genvar i;
generate
for ( i=0;i<pNUM_IF-1;i++ )
begin : genloop
always
begin
if( i == iADDRESS[pADDRESS_WIDTH-1 -: pDECODE_BITS])
begin : gen_mux
assign out = if_BUS[ i ];
end
end
end
endgenerate


modelsim still gives me an error i don't understand:
"LHS in procedural continuous assignment must be a variable: out."

and with this code

genvar i;
always
begin
generate
for ( i=0;i<pNUM_IF-1;i++ )
begin : genloop

if( i == iADDRESS[pADDRESS_WIDTH-1 -: pDECODE_BITS])
begin : gen_mux
assign out = if_BUS[ i ];
end
end
end
endgenerate

it gives the error: "near "generate": syntax error, unexpected generate"
but without using always it gives problem with the if condition (that must be a costant).