system verilog issue

[trescot@gmail.com]

Hi guys

I am a beginner in System Verilog. I have to test a "HALF_FULL" flag
which gets set when the write pointer points half the length of ram.
So if the ram is 1000 deep, as soon as write pointer points 500,
HALF_FULL is set. This flag remains set for the next 16 cycles(whether
write pointer value remains same or changes) and after that it should
be reset. Now say for example the flag gets reset after setting for 16
cycles, this event will not get triggered anymore no-matter how long
write pointer points to 500.
I have created an interface and hooked up my rtl top level output port
"HALF_FULL" pin(atb_if.HALF_FULL). I am creating an environment where
I'll be comparing the rtl pin with my SV generated status.
Can you guys give me an idea whether its viable or is there any way I
can improve it?


task ............
.........
// rwp_val is generated in another task
if (rwp_val == HALF_FULL && status_count<16 && event_seen_q ==
0)
begin
etb_half_full = 1 ;
if (atb_if.HALF_FULL != 1)
$display ($time,"Half_Full hardware event not triggered") ;
end
else if (rwp_val != HALF_FULL)
begin
etb_half_full = 0;
event_seen = 0;
end

if (etb_half_full_q && event_seen_q == 0)
begin
status_count++ ;
if (status_count == 16)
begin
if (atb_if.HALF_FULL != 0)
$display ($time,"The Half_Full O/P pin of ETB is not reset after
16 cycles") ;
else
begin
status_count = 0 ;
event_seen = 1 ;
end
end
end

// Registers
rwp_val_q = rwp_val ;
event_seen_q = event_seen ;